-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 08:10:50 03/21/2022 -- Design Name: -- Module Name: C:/Projekte/FPGA/divideby/tb_cegenerator.vhd -- Project Name: divideby -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: ClockEnableGenerator -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb_cegenerator IS END tb_cegenerator; ARCHITECTURE behavior OF tb_cegenerator IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ClockEnableGenerator generic ( DIVIDE_BY : integer := 5 -- default value ); PORT( clk_in : IN std_logic; clk_en_out : OUT std_logic; reset : IN std_logic ); END COMPONENT; --Inputs signal clk_in : std_logic := '0'; signal reset : std_logic := '1'; --Outputs signal clk_en_out : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ClockEnableGenerator GENERIC MAP ( DIVIDE_BY => 6 -- override the default value! ) PORT MAP ( clk_in => clk_in, clk_en_out => clk_en_out, reset => reset ); clk_in <= not clk_in after 5 ns; -- Stimulus process stim_proc: process begin reset <= '1'; wait for 10 ns; reset <= '0'; wait for 331 ns; end process; END;