library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity signal_generator is
	port(
		clock      : in  std_logic;
		reset      : in  std_logic;
		output     : out std_logic);
end entity;

architecture rtl of signal_generator is

signal counter     : unsigned(1 downto 0) := "00";

begin

process begin
	wait until falling_edge(clock);
	if reset = '0' then
		counter <= "00";
	else
		counter <= counter + 1;
	end if;
end process;

output <= '1' when counter(0) = '0' or (clock = '1' and counter = 1) else '0';

end rtl;