// Ghep khoi Tcam P=1;
`include "RegD.v"
`include "RegA.v"
`include "bram.v"
`include "PE01.v"
module TCAMsimple 
	# (
	    parameter integer  W_A = 8,
  	    parameter integer W_D = 10)
  	  ( 
  	  // cong 1 phuc vu viec ghi tu vao bo nho TCAM 
  	        input   wire        clks,
  		input   wire  [W_A-1:0] ADDR,
  		input   wire  [W_D-1:0] D,
  		input   wire          WE,
  		input 	wire 		enable,
  		//output  wire  [3: 0]	  add_out0
  	// cong 2 dua tu TCAM can tim kiem vao qua chan dia chi, xuat ra du lieu o chan du lieu 2
  		input   wire        clkp,
  		input   wire  [W_A-1:0] IW,
  		output  wire  [3: 0]	  add_out,
  		output  wire 		match
  		);//dia chi tu TCAM tim thay trong bo nho TCAM ao 
  		
  		
  		//input   wire          CLK1,
  		//input   wire  [W_A-1:0] ADDR1,
  		//input   wire  [W_D-1:0] D1,
  		//input   wire          WE1,
  		//output  wire  [3: 0]	  binary_out1);
 // Memory port to user logic 	
  // Khai bao Wire trung gian cho khoi TONG
  	//wire enable;
  	wire [W_A-1:0] ADDR0reg; // tin hieu trung gian dia chi ghi vao
  	wire  [W_D-1:0] D0reg;// du lieu ghi vao
  	//wire          WE;	
 	wire [W_A-1:0] ADDR1reg; // TU dau vao can tim kiem - INPUT WORD
  	//wire          WE1;
  	wire [W_D-1:0] Q; // RW bit dau ra chan du lieu 2 - tuong ung D1
  	wire [W_D-1:0] Matchword; // dau ra thanh ghi 4 //
  	wire [3:0] add_out1; // ket qua cuoi cung
  	//assign ADDR = ADDR0;
  	//assign D = D0;
  		// KHONG CAN THIET 
  	//assign WE = WE0;
  	//assign WE = WE1;
  
  //  USER LOGIC - Cac khoi con
  	RegD # (.W_A(8),
  		.W_D(10))
  	 reg1 ( 
  	 	.clk(clkp),
  	  	.enable (enable),
  	  	.Dinreg(D),
  	  	.Doreg(D0reg));
  	RegA # (.W_A(8),
  		.W_D(10))
 	 reg2 ( 	
 	 	.clk(clkp),
  	  	.enable (enable),
  	  	.Dinreg(ADDR),
  	  	.Doreg(ADDR0reg));
  	RegA # (.W_A(8),
  		.W_D(10))
  	  reg3 (
  	  	.clk(clkp),
  	  	.enable (enable),
  	  	.Dinreg(IW),
  	  	.Doreg(ADDR1reg));
  	RegD # (.W_A(8),
  		.W_D(10))
  	  reg4 (
  	  	.clk(clkp),
  	  	.enable (enable),
  	  	.Dinreg(Q),
  	  	.Doreg(Matchword));
  	PE01 
  	   # (.W_A(8),
  	      .W_D(10))
  	 logic1 (
  	  	.enable (enable),
  	  	.encoder_in(Matchword),
  	  	.binary_out(add_out1),
  	  	.match(match));
  	BRAM2 
  		# (.W_A(8),
  	     	 .W_D(10))
  	  logic2 (
  	  	.CLK0(clks),
  	  	.ADDR0(ADDR0reg),
  	  	.D0(D0reg),
  	  	.WE0(WE),
  	  	//.Q0(Matchword),
  	  	.CLK1(clks),
  	  	.ADDR1(ADDR1reg),
  	  	//.D1(D1),
  	  	.WE1(WE),
  	  	.Q1(Q));
  	assign add_out = add_out1 ;
 endmodule
 
 // XEM XET KHA NANG TEN TIN HIEU TRUNG VOI TEN CONG CUA KHOI TONG VA CAC KHOI CON, LIEU CO DUOC KHONG?