library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

-- OSC_in     = Oscillator Clock
-- PPS1_in    = 1PPS signal from GPS
-- qa         = Clock high
-- qb         = Clock low
-- PPS1_reset = Reset 1pps counter , active low
-- PPS1_out   = Output 1pps pulse

entity tb_ph_det is
end tb_ph_det;

architecture rtl of tb_ph_det is

component ph_det is
	generic
	(
		Osc_freq   : natural;
		Cnt_width  : natural
	);
	port
	(
		OSC_in     : in  std_logic;
		PPS1_in    : in  std_logic;
		PPS1_reset : in  std_logic; -- Has week pullup in cpld enabled , and therefore is Active low
		PPS1_out   : out std_logic;
		qa         : out std_logic;
		qb         : out std_logic;
		qab_xor    : out std_logic
	);
end component;

signal OSC_in      : std_logic:='0';
signal PPS1_in     : std_logic:='0';
signal PPS1_reset  : std_logic:='0';
signal PPS1_out    : std_logic:='0';
signal qa          : std_logic:='0';
signal qb          : std_logic:='0';
signal qab_xor     : std_logic:='0';

begin 
OSC_in     <= not OSC_in after 50 ns;
PPS1_in    <= not PPS1_in after 500000 us;
PPS1_reset <= '1';

UUT : ph_det
	generic map
	(
		Osc_freq   => 10000000,
		Cnt_width  => 24
	)
	port map
	(
		OSC_in     => OSC_in,
		PPS1_in    => PPS1_in,
		PPS1_reset => PPS1_reset,
		PPS1_out   => PPS1_out,
		qa         => qa,
		qb         => qb,
		qab_xor    => qab_xor
	);

end;