library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

-- OSC_in     = Oscillator Clock
-- PPS1_in    = 1PPS signal from GPS
-- qa         = Clock high
-- qb         = Clock low
-- PPS1_reset = Reset 1pps counter , active low
-- PPS1_out   = Output 1pps pulse

entity ph_det is
	generic
	(
		Osc_freq   : natural := 10000000;
		Cnt_width  : natural := 24
	);
	port
	(
		OSC_in     : in  std_logic;
		PPS1_in    : in  std_logic;
		PPS1_reset : in  std_logic; -- Has week pullup in cpld enabled , and therefore is Active low
		PPS1_out   : out std_logic;
		qa         : out std_logic;
		qb         : out std_logic;
		qab_xor    : out std_logic
	);
end ph_det;

architecture rtl of ph_det is

component d2 is
	port
	(
		inpu_c : in  std_logic;
		d_in   : in  std_logic;
		reset  : in  std_logic;
		q_out  : out std_logic 
	);
end component;

signal qa_int          : std_logic:='0';
signal qb_int          : std_logic:='0';
signal res             : std_logic:='0';
signal PPS1_reset_flag : std_logic:='0';
signal cnt             : unsigned(Cnt_width-1 downto 0):=(others => '0');
signal cntNext         : unsigned(Cnt_width-1 downto 0):=(others => '0');
signal cmp             : std_logic:='0';
signal cmpNext         : std_logic:='0';
signal dly             : std_logic:='0';
attribute keep         : boolean;
attribute keep of dly  : signal is true;

begin 

cmpNext <= '1' when cnt = OSC_freq-1 else '0';  
--cntNext <= to_unsigned(0, Cnt_width) when cmpNext='1' else cnt+1;  -- Ex1 - 55 LE used
--cntNext <= to_unsigned(0, Cnt_width) when cmpNext='1' or PPS1_reset_flag = '1' else cnt+1; -- Ex2 - 39 LE Used
cntNext <= to_unsigned(0, Cnt_width) when cmpNext='1' or PPS1_reset = '0' else cnt+1; --  Ex3 - 38 LE Used


process begin
	wait until rising_edge(OSC_in);
	PPS1_reset_flag <= not PPS1_reset;
	cnt             <= cntNext;
	cmp             <= cmpNext;
	pps1_out        <= cmp;
end process;

d0: d2 port map
	(
		inpu_c => Osc_in,
		reset  => res,
		d_in   => '1',
		q_out  => qa_int
	);

d1: d2 port map
	(
		inpu_c => PPS1_in,
		reset  => res,
		d_in   => '1',
		q_out  => qb_int
	);

dly <= not (qb_int and qa_int);
res <= not dly;

qa <= qa_int;
qb <= qb_int; 
qab_xor <= qa_int xor qb_int;

end;