library ieee;
use ieee.std_logic_1164.all;

entity d2 is
	port
	(
		inpu_c : in  std_logic;
		d_in   : in  std_logic;
		reset  : in  std_logic;
		q_out  : out std_logic 
	);
end d2;

architecture rtl of d2 is

signal q : std_logic:='0';

begin

q_out <= q;

dflop: process (inpu_c, reset) begin
	if reset = '1' then
		q <= '0';
	elsif  inpu_c 'event and inpu_c = '1' then
		q <= d_in;
	end if;
end process;

end;