-- file: d.vhd
------------------------------------------ 
--  D-Flip flop
--  
-- input is assigned to the output  
-- at the clock edge
--
-- By Ahmed Allam
-- October 8, 1999
-- University of Alberta, EE552.




library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 


entity d2 is 
	port (inpu_c, d_in, reset :in std_logic ;
          q_out  :buffer std_logic 
         ); 
end d2;       
	 
-- output is assigned to the input 
-- at the clcok edge
architecture archd2 of d2 is 
	begin 
	dflop:process (inpu_c, reset)


	begin 
          if reset = '1' then 
             q_out <= '0';
		  elsif  inpu_c 'event and inpu_c = '1' then 
    		  q_out <= d_in;
		   end if; 
	end process dflop; 
end archd2;