library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity Pseudo_random_generator is
	port( clk : in std_logic;
		 en : in std_logic;
		 output : out std_logic_vector(4 downto 0)
	);
end Pseudo_random_generator;

architecture Pseudo_random_generator_behavioral of Pseudo_random_generator is

signal lfsr: std_logic_vector(4 downto 0) := "00001";

begin

process begin
	wait until rising_edge(clk);
	if en = '1' then
		lfsr <= (lfsr(3) XOR lfsr(2) XOR lfsr(0)) & lfsr(4 downto 1);
	end if;
end process;

output <= lfsr;

end;