library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity display is
	port(
		clk : in std_logic;
		row_1 : in std_logic_vector(1 to 5);
		row_2 : in std_logic_vector(1 to 5);
		row_3 : in std_logic_vector(1 to 5);
		row_4 : in std_logic_vector(1 to 5);
		row_5 : in std_logic_vector(1 to 5);
		row_6 : in std_logic_vector(1 to 5);
		row_7 : in std_logic_vector(1 to 5);
		rows_out : out std_logic_vector(1 to 5);
		cols_out : out std_logic_vector(1 to 7)
	);
end entity display;

architecture display_arch of display is

signal counter : unsigned(5 downto 0):=(others => '0');

begin  

cols_out <= (others => '0');

process begin
	wait until rising_edge(clk);
	counter <= counter + 1;

	case counter(5 downto 3) is
		when "000" => rows_out <= row_1;
		when "001" => rows_out <= row_2;
		when "010" => rows_out <= row_3;
		when "011" => rows_out <= row_4;
		when "100" => rows_out <= row_5;
		when "101" => rows_out <= row_6;
		when "110" => rows_out <= row_7;
		when others => rows_out <= "00000";
	end case;
end process;

end;