library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity button is
	port(
		clk : in std_logic;
		input : in std_logic;
		output : out std_logic 
	);
end entity button;

architecture button_arch of button is

constant shift_register_length : integer := 10;
signal shift_register : std_logic_vector(shift_register_length-1 downto 0):=(others => '0');

begin

process begin
	wait until rising_edge(clk);
	shift_register <= shift_register(shift_register_length-1 downto 1) & input;
	output <= '0';
	if unsigned(shift_register) = 2**shift_register_length-1 then
		output <= '1';
		shift_register <= (others => '0');
	end if;
end process;

end;