library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity Pseudo_random_generator is
	port ( clk : in std_logic;
			 en : in std_logic;
			 output : out std_logic_vector (4 downto 0)
			 );
end Pseudo_random_generator;

architecture Pseudo_random_generator_behavioral of Pseudo_random_generator is

signal lfsr: std_logic_vector(4 downto 0) := "00001";

begin

	main_Pseudo_random_generator : process(clk)
	variable tmp : std_logic := '0';
	begin
		if rising_edge(clk) then
			if en = '1' THEN
				tmp := lfsr(3) XOR lfsr(2) XOR lfsr(0);
				lfsr <= tmp & lfsr(4 downto 1);
			end if;
		end if;
	end process;
	output <= lfsr;

end Pseudo_random_generator_behavioral;