library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity display is
	port(
			clk : in std_logic;
			row_1 : in std_logic_vector(1 to 5);
			row_2 : in std_logic_vector(1 to 5);
			row_3 : in std_logic_vector(1 to 5);
			row_4 : in std_logic_vector(1 to 5);
			row_5 : in std_logic_vector(1 to 5);
			row_6 : in std_logic_vector(1 to 5);
			row_7 : in std_logic_vector(1 to 5);
			
			rows_out : out std_logic_vector(1 to 5) := (others => '0');
			cols_out : buffer std_logic_vector(1 to 7) := (others => '0')
	);
end entity display;

architecture display_arch of display is
	constant mul_speed : integer range 0 to 7 := 7; --must be a multiple of 7--
	signal counter : integer range 0 to 7*mul_speed := 0;
	begin  
			with (counter mod mul_speed) select
				rows_out <= row_1 when 0,
								row_2 when 1,
								row_3 when 2,
								row_4 when 3,
								row_5 when 4,
								row_6 when 5,
								row_7 when 6,
								"00000" when others;		
			counter <= counter + 1 when rising_edge(clk);
			cols_out <= std_logic_vector(shift_right(unsigned(cols_out),1)) when rising_edge(clk);
	end architecture display_arch;