library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity button is
	port(
			clk : in std_logic;
			input : in std_logic;
			output : out std_logic 
		);
end entity button	;

architecture button_arch of button is
	constant dt_wait : integer range 0 to 10 := 10;
	signal counter : integer range 0 to dt_wait := 0;
	type state_type is (idle,waiting);
	signal state : state_type := waiting;

	begin
		main_button : process(clk, input)
		begin
			if rising_edge(clk) then
				case state is
					when idle => 
						if input = '1' then
							state <= waiting;
						else
							state <= idle;
						end if;
						output <= '0';
					when waiting =>
						if counter = dt_wait then
							counter <= 0;
							if input = '1' then
								output <= '1';
							end if;
						state <= idle;
						else
							counter <= counter + 1;
						end if;
					end case;		
			end if;
		end process main_button;
	end architecture button_arch;