LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY tb_sopeop IS
END tb_sopeop;
 
ARCHITECTURE behavior OF tb_sopeop IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT sopeop
    PORT(
         CLK : IN  std_logic;
         SOP : OUT  std_logic;
         EOP : OUT  std_logic;
         DATA_IN : IN  std_logic_vector(7 downto 0);
         DATA_OUT : OUT  std_logic_vector(7 downto 0);
         SCHALTER : IN  std_logic_vector(9 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal DATA_IN : std_logic_vector(7 downto 0) := (others => '0');
   signal SCHALTER : std_logic_vector(9 downto 0) := (others => '0');

 	--Outputs
   signal SOP : std_logic;
   signal EOP : std_logic;
   signal DATA_OUT : std_logic_vector(7 downto 0);

   signal cnt : unsigned (7 downto 0) := (others => '0');
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: sopeop PORT MAP (
          CLK => CLK,
          SOP => SOP,
          EOP => EOP,
          DATA_IN => DATA_IN,
          DATA_OUT => DATA_OUT,
          SCHALTER => SCHALTER
        );

   CLK <= not CLK after 5 ns;
   cnt <= cnt+1 when rising_edge(clk);
   DATA_IN <= std_logic_vector(cnt);

   -- Stimulus process
   stim_proc: process
   begin		
      SCHALTER <= "0000000000";
      wait for 1 us;
      SCHALTER <= "0000000001";
      wait for 1 us;
      SCHALTER <= "0000000010";
      wait for 1 us;
      SCHALTER <= "0000000011";
      wait for 1 us;
      SCHALTER <= "0000001000";
      wait for 5 us;
      SCHALTER <= "0000010000";
      wait for 20 us;
      SCHALTER <= "0000100000";
      wait for 50 us;
   end process;

END;