library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity sopeop is
  Port(
    CLK      : in  STD_LOGIC;
    SOP      : out STD_LOGIC;
    EOP      : out STD_LOGIC;
    DATA_IN  : in  STD_LOGIC_VECTOR(7 downto 0);
    DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);
    SCHALTER : in  STD_LOGIC_VECTOR(9 downto 0)  -- Bereich 0-1023
  );
end sopeop;

architecture Behavioral of sopeop is

signal cnt : integer range 0 to 1023;
signal len : integer range 0 to 1023; -- Paketlänge

begin
 
  len <= to_integer(unsigned(SCHALTER));
 
  process begin
     wait until rising_edge(clk);
     DATA_OUT <= DATA_IN; --> 1 Takt Latency, weil auch eop und sop 1 Takt Latency haben
     eop <= '0';
     sop <= '0';
     cnt <= cnt+1;
     if cnt = 0 then
        eop <= '1';
     end if;
     if cnt = len then
        cnt <= 0;
        sop <= '1';
     end if;
  end process;

end Behavioral;