/************************************************************\
 **  Copyright (c) 2011-2021 Anlogic, Inc.
 **  All Right Reserved.
\************************************************************/
/************************************************************\
 ** Log	:	This file is generated by Anlogic IP Generator.
 ** File	:	E:/LicheeTangFPGA/Projects/myterminal/LVDS_800x600_test2/al_ip/PLL_2.v
 ** Date	:	2021 04 06
 ** TD version	:	5.0.25341
\************************************************************/

///////////////////////////////////////////////////////////////////////////////
//	Input frequency:             40.000Mhz
//	Clock multiplication factor: 5
//	Clock division factor:       2
//	Clock information:
//		Clock name	| Frequency 	| Phase shift
//		C0        	| 100.000000MHZ	| 0  DEG     
//		C1        	| 40.000000 MHZ	| 0  DEG     
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 100 fs

module PLL_2(refclk,
		reset,
		stdby,
		extlock,
		clk0_out,
		clk1_out);

	input refclk;
	input reset;
	input stdby;
	output extlock;
	output clk0_out;
	output clk1_out;

	wire clk0_buf;

	EG_LOGIC_BUFG bufg_fbk( .i(clk0_buf), .o(clk0_out) );

	EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
		.DYNCFG("DISABLE"),
		.FIN("40.000"),
		.FEEDBK_MODE("ZERODELAY"),
		.FEEDBK_PATH("CLKC0_EXT"),
		.STDBY_ENABLE("ENABLE"),
		.PLLRST_ENA("ENABLE"),
		.SYNC_ENABLE("DISABLE"),
		.DERIVE_PLL_CLOCKS("DISABLE"),
		.GEN_BASIC_CLOCK("DISABLE"),
		.GMC_GAIN(2),
		.ICP_CURRENT(9),
		.KVCO(2),
		.LPF_CAPACITOR(1),
		.LPF_RESISTOR(8),
		.REFCLK_DIV(2),
		.FBCLK_DIV(5),
		.CLKC0_ENABLE("ENABLE"),
		.CLKC0_DIV(10),
		.CLKC0_CPHASE(9),
		.CLKC0_FPHASE(0),
		.CLKC1_ENABLE("ENABLE"),
		.CLKC1_DIV(25),
		.CLKC1_CPHASE(24),
		.CLKC1_FPHASE(0)	)
	pll_inst (.refclk(refclk),
		.reset(reset),
		.stdby(stdby),
		.extlock(extlock),
		.load_reg(1'b0),
		.psclk(1'b0),
		.psdown(1'b0),
		.psstep(1'b0),
		.psclksel(3'b000),
		.psdone(open),
		.dclk(1'b0),
		.dcs(1'b0),
		.dwe(1'b0),
		.di(8'b00000000),
		.daddr(6'b000000),
		.do({open, open, open, open, open, open, open, open}),
		.fbclk(clk0_out),
		.clkc({open, open, open, clk1_out, clk0_buf}));

endmodule