LIBRARY ieee; use ieee.numeric_std.all; use IEEE.std_logic_1164.all; ENTITY pulser_duo IS generic ( max_step_value : integer ); PORT( rst : in std_logic; clk : in std_logic; clear : in std_logic; current_step : in integer range 0 to max_step_value; offset1 : in integer range 0 to max_step_value; pulse_length1 : in integer range 0 to max_step_value; offset2 : in integer range 0 to max_step_value; pulse_length2 : in integer range 0 to max_step_value; output : out std_logic ); END ENTITY pulser_duo; ARCHITECTURE behavioural OF pulser_duo IS component pulser_solo generic ( max_step_value : integer ); PORT( rst : in std_logic; clk : in std_logic; clear : in std_logic; current_step : in integer range 0 to max_step_value; offset : in integer range 0 to max_step_value; pulse_length : in integer range 0 to max_step_value; output : out std_logic ); end component; signal output1, output2 : std_logic; begin inst_pulser_solo_1 : pulser_solo generic map ( max_step_value => max_step_value) port map ( rst => rst, clk => clk, clear => clear, current_step => current_step, offset => offset1, pulse_length => pulse_length1, output => output1); inst_pulser_solo_2 : pulser_solo generic map ( max_step_value => max_step_value) port map ( rst => rst, clk => clk, clear => clear, current_step => current_step, offset => offset2, pulse_length => pulse_length2, output => output2); output <= output1 or output2; end architecture behavioural;