LIBRARY IEEE; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_1164.ALL; ENTITY Counter IS PORT (q_out : OUT std_logic_vector(3 DOWNTO 0)); END ENTITY; ARCHITECTURE Behavioral OF Counter IS SIGNAL Q : std_logic_vector(3 DOWNTO 0) := "0000"; SIGNAL clk : std_logic := '0'; BEGIN clk <= NOT clk AFTER 10 ns; PROCESS (CLK, q(0), q(1), q(2), q(3)) BEGIN IF (clk = '1' AND clk'event) THEN q(0) <= NOT(q(0)); ELSE q(0) <= q(0); END IF; IF (q(0) = '1' AND q(0)'event) THEN q(1) <= NOT(q(1)); ELSE q(1) <= q(1); END IF; IF (q(1) = '1' AND q(1)'event) THEN q(2) <= NOT(q(2)); ELSE q(2) <= q(2); END IF; IF (q(2) = '1' AND q(2)'event) THEN q(3) <= NOT(q(3)); ELSE q(3) <= q(3); END IF; q_out <= Q; END PROCESS; END Behavioral;