LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb_flashled IS END tb_flashled; ARCHITECTURE behavior OF tb_flashled IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT flashled PORT( clk50M : IN std_logic; button : IN std_logic; led : OUT std_logic ); END COMPONENT; --Inputs signal clk50M : std_logic := '0'; signal button : std_logic := '0'; --Outputs signal led : std_logic; -- Clock period definitions constant clk50M_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: flashled PORT MAP ( clk50M => clk50M, button => button, led => led ); -- Clock process definitions clk50M_process :process begin clk50M <= '0'; wait for clk50M_period/2; clk50M <= '1'; wait for clk50M_period/2; end process; -- Stimulus process stim_proc: process begin wait for 2 ms; -- short press button <= '1'; wait for 500 us; button <= '0'; wait for 10 ms; -- short press bouncing button <= '1'; wait for 20 us; button <= '0'; wait for 30 us; button <= '1'; wait for 40 us; button <= '0'; wait for 60 us; button <= '1'; wait for 70 us; button <= '0'; wait for 90 us; button <= '1'; wait for 501 us; button <= '0'; wait for 10 ms; -- slightly longer press button <= '1'; wait for 1 ms; button <= '0'; wait for 10 ms; -- long press button <= '1'; wait for 20 ms; button <= '0'; wait for 10 ms; wait; end process; END;