`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:16:35 12/27/2019 
// Design Name: 
// Module Name:    Projet_Tech_SPI 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Projet_Tech_SPI(
     CLK_SPI,
     CS_SPI,
	  reset,
	  Count_Bit,
	  //Count_DateBit, 
	  //Count_DataBit, 
     SPI_Select
    ); 

//------------- Déclaration des entrées -----------------------------
input   CLK_SPI, CS_SPI, reset;
//------------- Déclaration des sorties ----------------------------
output   [1:0] SPI_Select;
output 	[3:0] Count_Bit;
//output   [1:0] Count_DateBit;
//output   [3:0] Count_DataBit;

//------------- Les ports d'entrées -------------------
wire    CLK_SPI, CS_SPI;
//------------- Les ports de sorties ------------------
reg     [1:0] SPI_Select;
reg	  [3:0] Count_Bit;
//reg     [1:0] Count_DateBit;
//reg     [3:0] Count_DataBit;

//------------- Les constantes internes --------------------------- 
reg i = 1;
reg j;
//assign CS_SPI = i;
parameter SIZE = 4;
parameter Idle = 4'b0001, Trans_FlagBit = 4'b0010, Trans_DateBit = 4'b0100, Trans_DataBit = 4'b1000 ;

//-------------Variables internes---------------------------
reg   [SIZE-1:0]          state        ;// Seq part of the FSM
reg   [SIZE-1:0]          next_state   ;// combo part of FSM
//----------Code startes Here------------------------
//assign next_state = fsm_function(state, Idle, Trans_FlagBit, Trans_DateBit, Trans_DataBit);


//---------- Logique séquentielle -----------------------------
always @ (posedge CLK_SPI)
begin : MEF_Seq
   if (reset == 1'b1) begin 
     state <=  #1  Idle;
   end else begin
     state <=  #1  next_state;
   end
end
//---------- Fin logique séquentielle -----------------------------

always @(state or CS_SPI)
begin : MEF_SPI
next_state = 4'b0001;


//Count_Bit <=4'b0011;
//Count_DateBit <= 2'b11;
//Count_DataBit <= 4'b1111;

case(state)
	Idle 			  : if(CS_SPI == 1'b0) begin
						 next_state = Idle;
						 end else if (CS_SPI == 1'b1 ) begin
						 next_state = Trans_FlagBit;
						 end 
						 
	Trans_FlagBit : if(CS_SPI == 1'b1) begin
						 next_state = Trans_DateBit;
						 Count_Bit =4'b0011; 
						 //i = 0;
						 //i=3;
						 //SPI_Select = 1;
						 end
						
						  
	Trans_DateBit : if(CS_SPI == 1'b1 && i!= 1'b0 ) begin
						 next_state = Trans_DateBit; 
						  Count_Bit =4'b0011;  
						  //assign j=i;
						 //i= i-1 
						 end else if(CS_SPI == 1'b1 && i==1'b0  ) begin 
						 next_state = Trans_DataBit;
						 Count_Bit <=4'b1100;
						 assign j=i;
						 end
						 
						/* if(CS_SPI == 1) begin  
							  if(i!=1'b0) begin
								  next_state = Trans_DateBit; 
								  Count_Bit =4'b0011;  
								  end else begin
								   next_state = Trans_DataBit;
									Count_Bit <=4'b1100;
									assign j=i;
								   end
						 end*/
						 
	Trans_DataBit : if(CS_SPI == 0 && Count_Bit != 4'b0000) begin
						 next_state = Trans_DataBit ;
						 assign i = Count_Bit;
						 //Count_Bit <= Count_Bit -1;
						 //i = i-1;
						 //assign CS_SPI = i; 
						 //SPI_Select = 2;
						 end else if(CS_SPI == 0 && Count_Bit == 4'b0000) begin
						 next_state = Trans_FlagBit;
						 i = 1;
						 //SPI_Select = 0;
						end 
						
	//default  	 : next_state = Idle;
	
	endcase; 
end
 



//---------- La logique de sortie -----------------------------
always @ (posedge CLK_SPI)
begin : Sorie_Logiq
if (reset == 1'b1) begin
  SPI_Select <= #1 2'b11;
end
else begin
  case(state)
    Idle : begin
						SPI_Select <= #1 2'b11;

               end
   Trans_FlagBit : begin
                   SPI_Select <= #1 2'b00;
						 //Count_Bit <=4'b0011;
						 
                end
   Trans_DateBit : begin
						SPI_Select <= #1 2'b01;
						Count_Bit <= Count_Bit -1;
						if(Count_Bit == 4'b0) begin
						i=0;
						end
						//Count_Bit <=4'b0011;

                end
	Trans_DataBit : begin
						SPI_Select <= #1 2'b10;
						Count_Bit <= Count_Bit -1;
						//Count_Bit <=4'b1100;

                end
   default : begin
						SPI_Select <= #1 2'b11;

                  end
  endcase
end
end // End Of Block OUTPUT_LOGIC

endmodule