Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity uart is
port(
clock_50: in std_logic;
sw: in std_logic_vector(9 downto 0);
key: in std_logic_vector(8 downto 0);
ledr: out std_logic_vector(9 downto 0);
ledg: out std_logic_vector(7 downto 0);
uart_txd: out std_logic;
uart_rxd: in std_logic

);
end uart;

Architecture main of uart is

SIGNAL TX_DATA: std_logic_vector(7 downto 0);
SIGNAL TX_START: std_logic:='0';
SIGNAL TX_BUSY: std_logic;
SIGNAL RX_DATA: std_logic_vector(7 downto 0);
SIGNAL RX_BUSY: std_logic;


component tx
PORT(
CLK:in std_logic;
START:in std_logic;
BUSY:out std_logic;
DATA: in std_logic_vector(7 downto 0);
TX_LINE:out std_logic
);
end component tx;
------------------------------------
component rx
PORT(
clk:in std_logic;
rx_line:in std_logic;
data:out std_logic_vector(7 downto 0);
busy: out std_logic
);
end component rx;
--------------------------------------


C1: tx port map (CLK=>CLOCK_50,START=>TX_START,BUSY=>TX_BUSY,DATA=>TX_DATA,TX_LINE=>UART_TXD);
C2: rx port map (CLOCK_50,uart_rxd,rx_data,rx_busy);

process(rx_busy)
begin
if(rx_busy'event and rx_busy='0') then
ledr(7 downto 0)<=rx_data;
end if;
end process;


process(CLOCK_50)
begin
  IF (CLOCK_50'EVENT and CLOCK_50='1') THEN
     IF (KEY(0)='0' and TX_BUSY='0') THEN
	   TX_DATA<=SW(7 DOWNTO 0);
		TX_START<='1';
		LEDG<=TX_DATA;
		ELSE
		TX_START<='0';
	  END IF;
  END IF;
END PROCESS;
END MAIN;