Version 4 SHEET 1 4596 5064 WIRE 704 416 704 336 WIRE 848 416 848 336 WIRE 704 576 704 496 WIRE 848 576 848 496 WIRE 1376 688 1072 688 WIRE 1744 688 1456 688 WIRE 1200 752 1152 752 WIRE 1296 752 1264 752 WIRE 1152 784 1152 752 WIRE 1536 800 1488 800 WIRE 1584 800 1536 800 WIRE 1680 800 1648 800 WIRE 1152 832 1152 784 WIRE 1392 832 1344 832 WIRE 1744 832 1744 688 WIRE 1744 832 1488 832 WIRE 944 848 864 848 WIRE 1072 848 1072 688 WIRE 1072 848 1024 848 WIRE 1120 848 1072 848 WIRE 1392 864 1184 864 WIRE 1664 864 1488 864 WIRE 1120 880 1056 880 WIRE 1344 896 1344 832 WIRE 1392 896 1344 896 WIRE 1536 896 1488 896 WIRE 1584 896 1536 896 WIRE 1664 896 1664 864 WIRE 1664 896 1648 896 WIRE 1680 896 1664 896 WIRE 1152 928 1152 896 WIRE 1152 960 1152 928 WIRE 1056 1056 1056 880 WIRE 1152 1056 1152 1024 WIRE 1152 1056 1056 1056 WIRE 1344 1056 1344 896 WIRE 1344 1056 1152 1056 WIRE 1056 1072 1056 1056 WIRE 688 1232 688 1152 WIRE 832 1232 832 1152 WIRE 688 1392 688 1312 WIRE 832 1392 832 1312 FLAG 1056 1072 0 FLAG 1680 800 0 FLAG 1680 896 0 FLAG 1296 752 0 FLAG 864 848 pos FLAG 688 1152 pos FLAG 832 1392 neg FLAG 832 1152 0 FLAG 688 1392 0 FLAG 704 336 Vsupply+ FLAG 848 576 Vsupply- FLAG 848 336 0 FLAG 704 576 0 FLAG 1392 800 pos FLAG 1536 800 Vsupply+ FLAG 1536 896 Vsupply- FLAG 1152 784 Vsupply+ FLAG 1152 928 Vsupply- SYMBOL Opamps\\AD712 1152 800 R0 SYMATTR InstName U9 SYMBOL AD633J 1440 848 R0 WINDOW 0 -43 73 Left 2 SYMATTR InstName AD633J SYMATTR SpiceModel "" SYMATTR Value AD633J SYMBOL res 1040 832 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R14 SYMATTR Value 10k SYMBOL cap 1648 784 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 100n SYMBOL cap 1648 880 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 100n SYMBOL res 1472 672 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R15 SYMATTR Value 10k SYMBOL cap 1264 736 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 100n SYMBOL cap 1168 1024 R180 WINDOW 0 45 35 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C4 SYMATTR Value 100n SYMBOL voltage 688 1216 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 2 SYMBOL voltage 832 1216 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 2 SYMBOL voltage 704 400 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 15 SYMBOL voltage 848 400 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value 15 TEXT 2784 488 Left 2 !* AD633J Analog Multiplier Macro Model\n* Description: Amplifier\n* Generic Desc: Bipolar, Multiplier, 4 Quadrant\n* Developed by: AAG/PMI\n* Revision History: 08/10/2012 - Updated to new header style\n* 1.0 (12/1993)\n* Copyright 1993, 2012 by Analog Devices\n*\n* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model\n* indicates your acceptance of the terms and provisions in the License Statement.\n*\n* BEGIN Notes:\n*\n* Not Modeled:\n*\n* Parameters modeled include:\n* This version of the AD633 analog multiplier model simulates the worst case\n* parameters of the 'J' grade. The worst case parameters used correspond\n* to those parameters in the data sheet.\n*\n* END Notes\n*\n* Node assignments\n* X1\n* | X2\n* | | Y1\n* | | | Y2\n* | | | | VNEG\n* | | | | | Z\n* | | | | | | W\n* | | | | | | | VPOS\n* | | | | | | | |\n.SUBCKT AD633J 1 2 3 4 5 6 7 8\n*\nEREF 100 0 POLY(2) 8 0 5 0 (0,0.5,0.5)\n*\n* X-INPUT STAGE & POLE AT 15 MHz\n*\nIBX1 1 0 DC 2E-6\nIBX2 2 0 DC 2E-6\nEOSX 10 1 POLY(1) (16,100) (30E-3,1)\nRX1A 10 11 5E6\nRX1B 11 2 5E6\n*\nGX 100 12 10 2 1E-6\nRX 12 100 1E6\nCX 12 100 1.061E-14\nVX1 8 13 DC 3.05\nDX1 12 13 DX\nVX2 14 5 DC 3.05\nDX2 14 12 DX\n*\n* COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz\n*\nECMX 15 100 11 100 10\nRCMX1 15 16 1E6\nCCMX 15 16 2.8421E-10\nRCMX2 16 100 1\n*\n* Y-INPUT STAGE & POLE AT 15 MHz\n*\nIBY1 3 0 DC 2E-6\nIBY2 4 0 DC 2E-6\nEOSY 20 3 POLY(1) (26,100) (30E-3,1)\nRY1A 20 21 5E6\nRY1B 21 4 5E6\n*\nGY 100 22 20 4 1E-6\nRY 22 100 1E6\nCY 22 100 1.061E-14\nVY1 8 23 DC 3.05\nDY1 22 23 DX\nVY2 24 5 DC 3.05\nDY2 24 22 DX\n*\n* COMMON-MODE GAIN NETWORK WITH ZERO AT 560 Hz\n*\nECMY 25 100 21 100 10\nRCMY1 25 26 1E6\nCCMY 25 26 2.8421E-10\nRCMY2 26 100 1\n*\n* Z-INPUT STAGE & POLE AT 15 MHz\n*\nIBZ1 7 0 DC 8E-7\nIBZ2 6 0 DC 8E-7\nRZ1 7 6 10E6\n*\nGZ 100 32 7 6 1E-6\nRZ2 32 100 1E6\nCZ 32 100 1.061E-14\nVZ1 8 33 DC 3.05\nDZ1 32 33 DX\nVZ2 34 5 DC 3.05\nDZ2 34 33 DX\n*\n* 50-MHz MULTIPLIER CORE & SUMMER\n*\nGXY 100 40 POLY(2) (12,100) (22,100) (0,0,0,0,0.1E-6)\nRXY 40 100 1E6\nCXY 40 100 3.1831E-15\n*\n* OP AMP INPUT STAGE\n*\nVOOS 59 40 DC 50E-3\nQ1 55 32 60 QX\nQ2 56 59 61 QX\nR1 8 55 3.1831E4\nR2 60 54 3.1313E4\nR3 8 56 3.1831E4\nR4 61 54 3.1313E4\nI1 54 5 1E-4\n*\n* GAIN STAGE & DOMINANT POLE AT 316.23 Hz\n*\nG1 100 62 55 56 3.141637E-5\nR5 62 100 1.0066E8\nC3 62 100 5E-12\nV1 8 63 DC 4.3399\nD1 62 63 DX\nV2 64 5 DC 4.3399\nD2 64 62 DX\n*\n* NEGATIVE ZERO AT 20 MHz\n*\nENZ 65 100 62 100 1E6\nRNZ1 65 66 1\nFNZ 65 66 VNC -1\nRNZ2 66 100 1E-6\nENC 67 0 65 66 1\nCNZ 67 68 7.9577E-9\nVNC 68 0 DC 0\n*\n* POLE AT 4 MHz\n*\nG2 100 69 66 100 1E-6\nR6 69 100 1E6\nC2 69 100 3.9789E-14\n*\n* OP AMP OUTPUT STAGE\n*\nFSY 8 5 POLY(2) VZC1 VZC2 (4.8286E-3,1,1)\nRDC 8 5 28E3\nGZC 100 73 72 69 11.623E-3\nVZC1 74 100 DC 0\nDZC1 73 74 DX\nVZC2 100 75 DC 0\nDZC2 75 73 DX\nVSC1 70 72 1.125\nDSC1 69 70 DX\nVSC2 72 71 1.125\nDSC2 71 69 DX\nGO1 72 8 8 69 11.623E-3\nRO1 8 72 86\nGO2 5 72 69 5 11.623E-3\nRO2 72 5 86\nLO 72 7 1E-7\n*\n* MODELS USED\n*\n.MODEL QX NPN(BF=1E4)\n.MODEL DX D(IS=1E-15)\n.ENDS AD633J TEXT 656 5048 Left 2 !.tran 0 500u 0 1u