// Cyclone IV at 50mhz
`timescale 1ns / 1ps
module VGA640x480(clk, reset, red, green, blue, vsync,hsync);
input clk,reset;
output vsync,hsync;
output reg [4:0] red;
output reg [5:0] green;
output reg [4:0] blue;  

reg [10:0] AH_SIZE=50;
reg axdir=1;
reg aydir=1;

//-------------------------------
// Load Spriterom from Internal
// Memory ROM: 1-Port
//-------------------------------

reg [6:0] address;
reg clock;
wire [15:0] q;

Spriterom u1(
	address,
	clock,
	q);

initial clock=0;

//-------------------------------
// VGA 800x600 Horizontal Values
//-------------------------------
parameter HTOTAL=1040;
parameter HZSYNC=120;
parameter HBACK_PORCH=64;
parameter HACTIVE=800;
parameter HFRONT_PORCH=56;
reg [10:0] H_SCAN; 
reg HPOLARITY;

//-----------------------------
// VGA 800x600 Vertical Values
//-----------------------------
parameter VTOTAL=666;
parameter VTSYNC=6;
parameter VBACK_PORCH=23;
parameter VACTIVE=600;
parameter VFRONT_PORCH=37;
reg [10:0] V_SCAN;
reg VPOLARITY;

//-----------------------------
// Load palette
reg [15:0] pal_memory [0:29]; //16 bits wide: 3 (R G B) x 10 colours = 30
initial $readmemh("Pal.txt", pal_memory);
//-----------------------------
// Horizontal Timings
//-----------------------------
always@(posedge clk)
begin
	//Horizontal Sync
	if(H_SCAN < HZSYNC)
		HPOLARITY <= 0;
	else 
		HPOLARITY <= 1;
   
	//End of line
	if(H_SCAN == HTOTAL)
		H_SCAN <= 0;
	else 
		H_SCAN <= H_SCAN + 1'b1;
end
assign hsync = HPOLARITY;

//-----------------------------
// Vertical Timings
//-----------------------------
always@(posedge clk)
begin
	//Vertical Sync
   	if(V_SCAN < VTSYNC)
		VPOLARITY <= 0;
	else 
		VPOLARITY <= 1;

	//Bottom of screen
   	if(H_SCAN == HZSYNC + HBACK_PORCH + HACTIVE)
		if(V_SCAN == VTOTAL)
			V_SCAN <= 0;
	else 
		V_SCAN <= V_SCAN + 1;
end
assign vsync = VPOLARITY;


always@(posedge clk)
begin
	if((H_SCAN > HZSYNC+HBACK_PORCH) && (V_SCAN > VTSYNC+VBACK_PORCH) && (H_SCAN < HZSYNC+HBACK_PORCH+HACTIVE+1) && (V_SCAN < VTSYNC+VBACK_PORCH+VACTIVE+1))
		begin
			if((H_SCAN > HZSYNC+HBACK_PORCH+100) && (V_SCAN > VTSYNC+VBACK_PORCH+50) && (H_SCAN < HZSYNC+HBACK_PORCH+110+1) && (V_SCAN < VTSYNC+VBACK_PORCH+60+1))
				begin
					red <= pal_memory[q[clock]*3]>>3;
					green <= pal_memory[(q[clock]*3)+1]>>2;
					blue <= pal_memory[(q[clock]*3)+2]>>3;
					clock <= clock + 1;
					if(clock == 100)
						clock<=0;
				end
			else
				begin
					red <= 0;
					green <= 0;
					blue <= 0;
				end
		end
else
		begin
			red <= 0;
			green <= 0;
			blue <= 0;
		end
end				
endmodule