use work.A208_pckgs.all; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DutyPhaseMod is port ( rst : in std_logic; GLA : in std_logic; -- GLA is 36x faster than target frequency tx_en0 : in std_logic; -- tx_en0/1 synchronize the start of the clock signal, otherwise tx_en1 : in std_logic; -- the first EX_out signal will miss the first GLA cycle and -- cause noise at the beginning of the TX period txrx0 : in std_logic; -- txrx0/1 provide a reference to maintain synchronization of txrx1 : in std_logic; -- the EX and DM clocks during both the TX and the RX periods and -- spans from the start of TX_BEGIN through to RX_END EXDuty : in std_logic_vector(3 downto 0); -- the number of GLA clock cycles for the EX duty cycle -- 10 clock cycles = 50% duty cycle DMDuty : in std_logic_vector(3 downto 0); -- the number of GLA clock cycles for the DM duty cycle DMDelay : in std_logic_vector(4 downto 0); -- the number of GLA clock cycles for the DM phase delay EX_out : out std_logic; DM_out : out std_logic -- EXctr_out : out std_logic_vector (5 downto 0); -- for debugging (display on LED display) -- DMctr_out : out std_logic_vector (5 downto 0) -- for debugging (display on LED display) ); end entity; architecture behavioral of DutyPhaseMod is signal iGLA : std_logic; signal iFREQlen : natural range 0 to 34; signal iEXctr : natural; begin --*************************************************************************************** --* Generate the EX clock on the rising_edge of the high-speed (GLA) clock --*************************************************************************************** process (rst, GLA) variable iEX_out : std_logic; begin case FW_FREQ is when F_46 => iFREQlen <= 34; -- when F_82 => -- iFREQlen <= 18; end case; if rst = '1' then iEXctr <= 0; elsif ( txrx0 = '1' or txrx1 = '1' ) then if rising_edge(GLA) then if iEXctr <= unsigned(EXDuty) then iEX_out := '1'; iEXctr <= iEXctr + 1; elsif iEXctr <= iFREQlen then iEX_out := '0'; iEXctr <= iEXctr + 1; else iEXctr <= 0; end if; end if; else iEX_out := '0'; iEXctr <= 0; end if; EX_out <= iEX_out and ( tx_en0 or tx_en1); end process; --*************************************************************************************** --* Generate the DM clock on the falling_edge of the high-speed (GLA) clock. This will --* presumably allow enough time for the iEXctr to be set before evaluating in this process. --* Previously the logic for this section was combined with the EX clock but at high-speeds --* the DM signals were not getting asserted properly. --*************************************************************************************** process (rst, GLA) variable iDM_out : std_logic; variable iDMctr : natural range 0 to 34; begin case FW_FREQ is when F_46 => iFREQlen <= 34; when F_82 => iFREQlen <= 18; end case; if rst = '1' then iDMctr := 0; elsif ( txrx0 = '1' or txrx1 = '1' ) then if falling_edge(GLA) then if iEXctr = unsigned(DMDelay) then iDM_out := '1'; iDMctr := 1; elsif iDMctr <= unsigned(DMDuty) then iDM_out := '1'; iDMctr := iDMctr + 1; elsif iDMctr <= iFREQlen then iDM_out := '0'; iDMctr := iDMctr + 1; else iDM_out := '0'; iDMctr := 0; end if; end if; else iDM_out := '0'; end if; DM_out <= iDM_out and ( txrx0 or txrx1 ); end process; end behavioral;