---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 23:00:49 05/04/2018 -- Design Name: -- Module Name: oneshot - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity oneshot is port ( clk : in STD_LOGIC; ce : in STD_LOGIC; trigger : in STD_LOGIC; delay : in STD_LOGIC_VECTOR (7 downto 0); pulse : out STD_LOGIC :='0'); end oneshot; architecture Behavioral of oneshot is signal count: INTEGER range 0 to 255; -- count variable signal flag : STD_LOGIC := '0'; -- count variable begin process (flag,clk,delay) begin -- wait for trigger leading edge if trigger = '1' then count <= to_integer(unsigned(delay)); elsif rising_edge(clk) then if count > 0 then pulse <= '1'; count <= count - 1; else pulse <= '0'; --flag <='0'; end if; end if; end process; end Behavioral;