---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:18:25 09/12/2017 -- Design Name: -- Module Name: DAC - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity DAC is port( clk_50 :in std_logic; SPI_MISO :in std_logic; SPI_MOSI :out std_logic; SPI_SCK :inout std_logic; SPI_SS_B :out std_logic; --DEACTIVATION SF_CE0 :out std_logic; --DEACTIVATION FPGA_INIT_B :out std_logic; --DEACTIVATION DAC_CS :out std_logic := '1'); end DAC; architecture Behavioral of DAC is type state_type is (SET, SENDBIT, THEEND); signal state: state_type := SET; signal risingedge :std_logic := '1'; signal clk_counter :integer range 0 to 33 := 0; signal dacdata: signed(32 downto 0) := (others => '0'); signal dacsend : signed(11 downto 0) := (others => '0'); signal daccounter: integer range 0 to 32; begin --This is a clock devider in order to get a 2MHz clock. process(clk_50) begin if rising_edge(clk_50) then if (clk_counter = 33) then risingedge <= risingedge xor '1'; clk_counter <= 0; else clk_counter <= clk_counter + 1; end if; end if; end process; SPI_SCK <= risingedge; --This is in order to deactivate other functions that the SPI has. SPI_SS_B <= '0'; SF_CE0 <= '1'; FPGA_INIT_B <= '1'; process(SPI_SCK) begin if rising_edge(SPI_SCK) then case state is when SET => dacdata <= "00000000" & "0011" & "1111" & dacsend & "00000"; -- (x8)zeros + (x4)command + (x4)adress + (x12)data + (x5)zeros daccounter <= 32; DAC_CS <= '0'; state <= SENDBIT; when SENDBIT => if daccounter = 0 then state <= THEEND; elsif daccounter > 0 then SPI_MOSI <= dacdata(daccounter); daccounter <= daccounter - 1; state <= SENDBIT; end if; when THEEND => DAC_CS <= '1'; dacsend <= (others => '0'); dacdata <= (others => '0'); state <= SET ; end case; end if; end process; end Behavioral;