library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_design_1 is 
end test_design_1;


architecture TB of test_design_1 is

component design_1 is
port (
  BCLK_1 : out STD_LOGIC;
  DDR_addr : inout STD_LOGIC_VECTOR (14 downto 0);
  DDR_ba : inout STD_LOGIC_VECTOR (2 downto 0);
  DDR_cas_n : inout STD_LOGIC;
  DDR_ck_n : inout STD_LOGIC;
  DDR_ck_p : inout STD_LOGIC;
  DDR_cke : inout STD_LOGIC;
  DDR_cs_n : inout STD_LOGIC;
  DDR_dm : inout STD_LOGIC_VECTOR (3 downto 0);
  DDR_dq : inout STD_LOGIC_VECTOR (31 downto 0);
  DDR_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
  DDR_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
  DDR_odt : inout STD_LOGIC;
  DDR_ras_n : inout STD_LOGIC;
  DDR_reset_n : inout STD_LOGIC;
  DDR_we_n : inout STD_LOGIC;
  FCLK_CLK1 : out STD_LOGIC;
  FCLK_CLK1_1 : out STD_LOGIC;
  FIXED_IO_ddr_vrn : inout STD_LOGIC;
  FIXED_IO_ddr_vrp : inout STD_LOGIC;
  FIXED_IO_mio : inout STD_LOGIC_VECTOR (53 downto 0);
  FIXED_IO_ps_clk : inout STD_LOGIC;
  FIXED_IO_ps_porb : inout STD_LOGIC;
  FIXED_IO_ps_srstb : inout STD_LOGIC;
  GPIO2_1_tri_i : in STD_LOGIC_VECTOR (0 to 0);
  GPIO2_1_tri_o : out STD_LOGIC_VECTOR (0 to 0);
  GPIO2_1_tri_t : out STD_LOGIC_VECTOR (0 to 0);
  GPIO_1_tri_i : in STD_LOGIC_VECTOR (1 downto 0);
  GPIO_1_tri_o : out STD_LOGIC_VECTOR (1 downto 0);
  GPIO_1_tri_t : out STD_LOGIC_VECTOR (1 downto 0);
  IIC_1_scl_i : in STD_LOGIC;
  IIC_1_scl_o : out STD_LOGIC;
  IIC_1_scl_t : out STD_LOGIC;
  IIC_1_sda_i : in STD_LOGIC;
  IIC_1_sda_o : out STD_LOGIC;
  IIC_1_sda_t : out STD_LOGIC;
  LRCLK_1 : out STD_LOGIC;
  SDATA_I : in STD_LOGIC;
  SDATA_O_1 : out STD_LOGIC
);
end component design_1;

signal BCLK_1 : STD_LOGIC;
signal DDR_addr : STD_LOGIC_VECTOR (14 downto 0);
signal DDR_ba : STD_LOGIC_VECTOR (2 downto 0);
signal DDR_cas_n : STD_LOGIC;
signal DDR_ck_n : STD_LOGIC;
signal DDR_ck_p : STD_LOGIC;
signal DDR_cke : STD_LOGIC;
signal DDR_cs_n : STD_LOGIC;
signal DDR_dm : STD_LOGIC_VECTOR (3 downto 0);
signal DDR_dq : STD_LOGIC_VECTOR (31 downto 0);
signal DDR_dqs_n : STD_LOGIC_VECTOR (3 downto 0);
signal DDR_dqs_p : STD_LOGIC_VECTOR (3 downto 0);
signal DDR_odt : STD_LOGIC;
signal DDR_ras_n : STD_LOGIC;
signal DDR_reset_n : STD_LOGIC;
signal DDR_we_n : STD_LOGIC;
signal FCLK_CLK1 : STD_LOGIC;
signal FCLK_CLK1_1 : STD_LOGIC;
signal FIXED_IO_ddr_vrn : STD_LOGIC;
signal FIXED_IO_ddr_vrp : STD_LOGIC;
signal FIXED_IO_mio : STD_LOGIC_VECTOR (53 downto 0);
signal FIXED_IO_ps_clk : STD_LOGIC;
signal FIXED_IO_ps_porb : STD_LOGIC;
signal FIXED_IO_ps_srstb : STD_LOGIC;
signal GPIO2_1_tri_i : STD_LOGIC_VECTOR (0 to 0);
signal GPIO2_1_tri_o : STD_LOGIC_VECTOR (0 to 0);
signal GPIO2_1_tri_t : STD_LOGIC_VECTOR (0 to 0);
signal GPIO_1_tri_i : STD_LOGIC_VECTOR (1 downto 0);
signal GPIO_1_tri_o : STD_LOGIC_VECTOR (1 downto 0);
signal GPIO_1_tri_t : STD_LOGIC_VECTOR (1 downto 0);
signal IIC_1_scl_i : STD_LOGIC;
signal IIC_1_scl_o : STD_LOGIC;
signal IIC_1_scl_t : STD_LOGIC;
signal IIC_1_sda_i : STD_LOGIC;
signal IIC_1_sda_o : STD_LOGIC;
signal IIC_1_sda_t : STD_LOGIC;
signal LRCLK_1 : STD_LOGIC;
signal SDATA_I : STD_LOGIC;
signal SDATA_O_1 : STD_LOGIC;
begin

DUT: component design_1 port map (
  BCLK_1 => BCLK_1,
  DDR_addr => DDR_addr,
  DDR_ba => DDR_ba,
  DDR_cas_n => DDR_cas_n,
  DDR_ck_n => DDR_ck_n,
  DDR_ck_p => DDR_ck_p,
  DDR_cke => DDR_cke,
  DDR_cs_n => DDR_cs_n,
  DDR_dm => DDR_dm,
  DDR_dq => DDR_dq,
  DDR_dqs_n => DDR_dqs_n,
  DDR_dqs_p => DDR_dqs_p,
  DDR_odt => DDR_odt,
  DDR_ras_n => DDR_ras_n,
  DDR_reset_n => DDR_reset_n,
  DDR_we_n => DDR_we_n,
  FCLK_CLK1 => FCLK_CLK1,
  FCLK_CLK1_1 => FCLK_CLK1_1,
  FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
  FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
  FIXED_IO_mio => FIXED_IO_mio,
  FIXED_IO_ps_clk => FIXED_IO_ps_clk,
  FIXED_IO_ps_porb => FIXED_IO_ps_porb,
  FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
  GPIO2_1_tri_i => GPIO2_1_tri_i,
  GPIO2_1_tri_o => GPIO2_1_tri_o,
  GPIO2_1_tri_t => GPIO2_1_tri_t,
  GPIO_1_tri_i => GPIO_1_tri_i,
  GPIO_1_tri_o => GPIO_1_tri_o,
  GPIO_1_tri_t => GPIO_1_tri_t,
  IIC_1_scl_i => IIC_1_scl_i,
  IIC_1_scl_o => IIC_1_scl_o,
  IIC_1_scl_t => IIC_1_scl_t,
  IIC_1_sda_i => IIC_1_sda_i,
  IIC_1_sda_o => IIC_1_sda_o,
  IIC_1_sda_t => IIC_1_sda_t,
  LRCLK_1 => LRCLK_1,
  SDATA_I => SDATA_I,
  SDATA_O_1 => SDATA_O_1
);
clocksim: process
begin
 FCLK_CLK1 <= '0';
wait for 10 ns;
 FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
FCLK_CLK1 <= '0';
wait for 10 ns;
 FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;
 FCLK_CLK1 <= '0';
wait for 10 ns;
FCLK_CLK1 <= '1';
wait for 10 ns;

end process clocksim;


input_test: process
begin
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
wait for 10 ns;
SDATA_I <= '1';
wait for 10 ns;
SDATA_I <= '0';
wait for 10 ns;
SDATA_I <= '0';
wait;
end process input_test; 

end TB;