library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

ENTITY writeDummy IS
	PORT (
		clkIn 	: in 		std_logic;		
		sclIO		: inout  std_logic;                -- i2c clock line 
		sdaIO		: inout 	std_logic;               -- i2c data line
		led		: out std_logic_vector(4 DOWNTO 0);
		
		test 		: out std_logic
	);
END ENTITY writeDummy;
USE WORK.ALL;


ARCHITECTURE behave OF writeDummy IS

	COMPONENT i2c_controller_top IS
		PORT (
			clk 		: in std_logic;
			dataIn	: in std_logic_vector(7 DOWNTO 0);
			dataOut	: out std_logic_vector(7 DOWNTO 0);
			rst 		: in std_logic;
			rw			: in std_logic; --Set to write or read data
			ready 	: out std_logic; -- Is set when ready for new data
			tip 		: out std_logic; -- Transfer is in progress
			last 		: in std_logic; -- Set when sending the last byte 
			
			scl     	: inout  std_logic;                -- i2c clock line 
			sda     	: inout std_logic                -- i2c data line
		);
	END COMPONENT i2c_controller_top;
	
	SIGNAL dataInTmp	: std_logic_vector(7 DOWNTO 0);
	SIGNAL dataOutTmp	: std_logic_vector(7 DOWNTO 0);
	SIGNAL rstTmp		: std_logic;
	SIGNAL rwTmp		: std_logic; --Set to write or read data
	SIGNAL readyTmp	: std_logic; -- Is set when ready for new data
	SIGNAL tipTmp 		: std_logic; -- Transfer is in progress
	SIGNAL lastTmp 	: std_logic; -- Set when sending the last byte
	
	
	TYPE TSTATE IS(Idle0, SetAddr, Wait0, Wait1, SetData);
	SIGNAL state: TSTATE := Idle0;
	
	signal t : std_logic := '0';
	
	BEGIN
		i2cC: i2c_controller_top PORT MAP(
			clk 		=> clkIn,
			dataIn	=> dataInTmp,
			dataOut	=> dataOutTmp,
			rst 		=> rstTmp,
			rw			=> rwTmp,
			ready 	=> readyTmp,
			tip 		=> tipTmp,
			last 		=> lastTmp,
			
			scl     	=> sclIO,               -- i2c clock line 
			sda     	=> sdaIO
		);
		
		PROCESS (clkIn)
			BEGIN	
				IF rising_edge(clkIn) THEN
					if t = '1' then
						test <= '0';
						t <= '0';
					else
						test <= '1';
						t <= '1';
					end if;
					CASE state IS
						WHEN Idle0 =>
							IF tipTmp = '0' AND readyTmp = '1' THEN
								state <= SetAddr;
							END IF;
						WHEN SetAddr =>
							state <= Wait0;
						WHEN Wait0 =>
							IF tipTmp = '1' AND readyTmp = '1' THEN
								state <= SetData;
							END IF;
						WHEN SetData =>
							state <= Wait1;
						WHEN Wait1 =>
							IF tipTmp = '0' AND readyTmp = '1' THEN
								state <= Idle0;
							END IF;
						END CASE;
				END IF;
		END PROCESS;
		
		PROCESS (state)
			BEGIN
				CASE state IS
					WHEN Idle0 =>
						led <= "10000";
					WHEN SetAddr =>
						dataInTmp <= "00010000";
						rwTmp <= '1';
						led <= "01000";
					WHEN  Wait0 =>
						led <= "00100";
					WHEN SetData =>
						dataInTmp <= "11111111";
						rwTmp <= '1';
						lastTmp <= '1';
						led <= "00010";
					WHEN Wait1 =>
						led <= "00001";
				END CASE;
		END PROCESS;
						
			
	
END ARCHITECTURE behave;