library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity i2c_avalonwrap is
  
  port (
-- ports to outer world
    scl           : inout std_logic;
    sda           : inout std_logic;
-- ports to avalon
    clock         : in    std_logic;
    reset_n       : in    std_logic;
    waitrequest_n : out   std_logic;                     -- wb_ack_o
    readdata      : out   std_logic_vector(7 downto 0);  -- wb_dat_o
    address       : in    std_logic_vector(2 downto 0);  -- wb_adr_i
    writedata     : in    std_logic_vector(7 downto 0);  -- wb_dat_i
    write         : in    std_logic;                     -- wb_we_i
    chipselect    : in    std_logic                    -- wb_stb_i, wb_cyc_i
    );

end i2c_avalonwrap;

architecture behave of i2c_avalonwrap is
  
  component i2c_master_top
    port (
      wb_clk_i     : in  std_logic;
      wb_rst_i     : in  std_logic;
      arst_i       : in  std_logic;
      wb_adr_i     : in  unsigned(2 downto 0);
      wb_dat_i     : in  std_logic_vector(7 downto 0);
      wb_dat_o     : out std_logic_vector(7 downto 0);
      wb_we_i      : in  std_logic;
      wb_stb_i     : in  std_logic;
      wb_cyc_i     : in  std_logic;
      wb_ack_o     : out std_logic;
      scl_pad_i    : in  std_logic;
      scl_pad_o    : out std_logic;
      scl_padoen_o : out std_logic;
      sda_pad_i    : in  std_logic;
      sda_pad_o    : out std_logic;
      sda_padoen_o : out std_logic);
  end component;

  
  signal address_i     : unsigned(2 downto 0);
  signal scl_pad_i     : std_logic;
  signal scl_pad_o     : std_logic;
  signal scl_padoen_o  : std_logic;
  signal sda_pad_i     : std_logic;
  signal sda_pad_o     : std_logic;
  signal sda_padoen_o  : std_logic;
  signal gnd           : std_logic;
  
begin  -- behave

  
  gnd <= '0';
  scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
  sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
  scl_pad_i <= scl;
  sda_pad_i <= sda;
  address_i <= unsigned(address);
  
  i2c_master_top_1: i2c_master_top
    port map (
      wb_clk_i     => clock,
      wb_rst_i     => gnd,
      arst_i       => reset_n,
      wb_adr_i     => address_i,
      wb_dat_i     => writedata,
      wb_dat_o     => readdata,
      wb_we_i      => write,
      wb_stb_i     => chipselect,
      wb_cyc_i     => chipselect,
      wb_ack_o     => waitrequest_n,
      scl_pad_i    => scl_pad_i,
      scl_pad_o    => scl_pad_o,
      scl_padoen_o => scl_padoen_o,
      sda_pad_i    => sda_pad_i,
      sda_pad_o    => sda_pad_o,
      sda_padoen_o => sda_padoen_o);


end behave;