---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:58:09 04/22/2017 -- Design Name: -- Module Name: fivebit - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fivebit is Port ( EKS : out STD_LOGIC_VECTOR (4 downto 0); res : in STD_LOGIC; clockk : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (2 downto 0); INP : in STD_LOGIC_VECTOR (4 downto 0)); end fivebit; architecture Behavioral of fivebit is COMPONENT D_flip_flop Port ( D : in STD_LOGIC; clk : in STD_LOGIC; clear : in STD_LOGIC; Q : out STD_LOGIC); end COMPONENT; COMPONENT MUX_8x1 Port ( I : in STD_LOGIC_VECTOR (7 downto 0); S : in STD_LOGIC_VECTOR (2 downto 0); Y : out STD_LOGIC); end COMPONENT; COMPONENT half_adder Port ( A : in STD_LOGIC; B : in STD_LOGIC; Sout : out STD_LOGIC; C : out STD_LOGIC); end COMPONENT; signal si0,si1,si2,si3,si4,car0,car1,car2,car3,car4,sum0,sum1,sum2,sum3,sum4:std_logic; begin MUX_8x1_1: MUX_8x1 PORT MAP ( I(0) =>INP(0), I(1) =>INP(1), I(2) =>'0', I(3) =>INP(1), I(4) =>INP(4), I(5) =>not(INP(0)), I(6) =>sum0, I(7) =>'0', S(0) =>SEL(0), S(1) =>SEL(1), S(2) =>SEL(2), Y =>si0 ); MUX_8x1_2: MUX_8x1 PORT MAP ( I(0) =>INP(1), I(1) =>INP(2), I(2) =>INP(0), I(3) =>INP(2), I(4) =>INP(0), I(5) =>not(INP(1)), I(6) =>sum1, I(7) =>'0', S(0) =>SEL(0), S(1) =>SEL(1), S(2) =>SEL(2), Y =>si1 ); MUX_8x1_3: MUX_8x1 PORT MAP ( I(0) =>INP(2), I(1) =>INP(3), I(2) =>INP(1), I(3) =>INP(3), I(4) =>INP(1), I(5) =>not(INP(2)), I(6) =>sum2, I(7) =>'0', S(0) =>SEL(0), S(1) =>SEL(1), S(2) =>SEL(2), Y =>si2 ); MUX_8x1_4: MUX_8x1 PORT MAP ( I(0) =>INP(3), I(1) =>INP(4), I(2) =>INP(2), I(3) =>INP(4), I(4) =>INP(2), I(5) =>not(INP(3)), I(6) =>sum3, I(7) =>'0', S(0) =>SEL(0), S(1) =>SEL(1), S(2) =>SEL(2), Y =>si3 ); MUX_8x1_5: MUX_8x1 PORT MAP ( I(0) =>INP(4), I(1) =>'0', I(2) =>INP(3), I(3) =>INP(0), I(4) =>INP(3), I(5) =>not(INP(4)), I(6) =>sum4, I(7) =>'0', S(0) =>SEL(0), S(1) =>SEL(1), S(2) =>SEL(2), Y =>si4 ); D_flip_flop_1: D_flip_flop PORT MAP ( D =>si0, clk =>clockk, clear =>not(res), Q =>EKS(0) ); D_flip_flop_2: D_flip_flop PORT MAP ( D =>si1, clk =>clockk, clear =>not(res), Q =>EKS(1) ); D_flip_flop_3: D_flip_flop PORT MAP ( D =>si2, clk =>clockk, clear =>not(res), Q =>EKS(2) ); D_flip_flop_4: D_flip_flop PORT MAP ( D =>si3, clk =>clockk, clear =>not(res), Q =>EKS(3) ); D_flip_flop_5: D_flip_flop PORT MAP ( D =>si4, clk =>clockk, clear =>not(res), Q =>EKS(4) ); Half_adder_1: half_adder PORT MAP ( A =>'1', B =>not(INP(0)), Sout =>sum0, C =>car0 ); Half_adder_2: half_adder PORT MAP ( A =>car0, B =>not(INP(1)), Sout =>sum1, C =>car1 ); Half_adder_3: half_adder PORT MAP ( A =>car1, B =>not(INP(2)), Sout =>sum2, C =>car2 ); Half_adder_4: half_adder PORT MAP ( A =>car2, B =>not(INP(3)), Sout =>sum3, C =>car3 ); Half_adder_5: half_adder PORT MAP ( A =>car3, B =>not(INP(4)), Sout =>sum4, C =>car4 ); end Behavioral;