---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:03:23 04/05/2017 -- Design Name: -- Module Name: prescaler - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity prescaler is Port ( clk_in : in STD_LOGIC; clk_out : out STD_LOGIC; rst : in STD_LOGIC); end prescaler; architecture Behavioral of prescaler is signal co : std_logic; begin process(clk_in,rst) variable count: integer range 0 to 25_000_000; begin if rst='1' then co<='0'; count:=0; elsif clk_in'event and clk_in='1' then count:=count+1; if count= 25_000_000 then count:=0 co <= not co; end if; end if; end process; clk_out <= co; end Behavioral;