library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY sdram IS
port(

CLOCK_50: IN STD_LOGIC;
---------------------sdram
DRAM_ADDR: OUT STD_LOGIC_VECTOR(12 downto 0);
DRAM_BA: OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_CAS_N: OUT STD_LOGIC;
DRAM_CKE: OUT STD_LOGIC;
DRAM_CLK: OUT STD_LOGIC;
DRAM_CS_N: OUT STD_LOGIC;
DRAM_DQ: INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_RAS_N: OUT STD_LOGIC;
DRAM_WE_N: OUT STD_LOGIC;
DRAM_LDQM,DRAM_UDQM: OUT STD_LOGIC;
LED1, LED2, LED3: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
OUTPUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);

end sdram;

architecture  main of sdram is
TYPE STAGES IS (ST0,ST1,ST2);
SIGNAL BUFF_CTRL: STAGES:=ST0;


SIGNAL SDRAM_ADDR: STD_LOGIC_VECTOR(24 downto 0);
SIGNAL SDRAM_BE_N: STD_LOGIC_VECTOR(1 downto 0);
SIGNAL SDRAM_CS: STD_LOGIC;
SIGNAL SDRAM_RDVAL,SDRAM_WAIT:STD_LOGIC;
SIGNAL SDRAM_RE_N,SDRAM_WE_N: STD_LOGIC;
SIGNAL SDRAM_READDATA,SDRAM_WRITEDATA: STD_LOGIC_VECTOR(15 downto 0);
SIGNAL DATA: STD_LOGIC_VECTOR(7 downto 0);
SIGNAL DRAM_DQM : STD_LOGIC_VECTOR(1 downto 0);

-----------------------------------------------------
signal counter : integer range 0 to 1000;
signal clk143: std_logic;

    component clocky is
        port (
            clk_clk             : in    std_logic                     := 'X';             -- clk
            reset_reset_n       : in    std_logic                     := 'X';             -- reset_n
            wire_addr           : out   std_logic_vector(12 downto 0);                    -- addr
            wire_ba             : out   std_logic_vector(1 downto 0);                     -- ba
            wire_cas_n          : out   std_logic;                                        -- cas_n
            wire_cke            : out   std_logic;                                        -- cke
            wire_cs_n           : out   std_logic;                                        -- cs_n
            wire_dq             : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
            wire_dqm            : out   std_logic_vector(1 downto 0);                     -- dqm
            wire_ras_n          : out   std_logic;                                        -- ras_n
            wire_we_n           : out   std_logic;                                        -- we_n
            sdram_address       : in    std_logic_vector(24 downto 0) := (others => 'X'); -- address
            sdram_byteenable_n  : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- byteenable_n
            sdram_chipselect    : in    std_logic                     := 'X';             -- chipselect
            sdram_writedata     : in    std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
            sdram_read_n        : in    std_logic                     := 'X';             -- read_n
            sdram_write_n       : in    std_logic                     := 'X';             -- write_n
            sdram_readdata      : out   std_logic_vector(15 downto 0);                    -- readdata
            sdram_readdatavalid : out   std_logic;                                        -- readdatavalid
            sdram_waitrequest   : out   std_logic;                                        -- waitrequest
            clk143_clk          : out   std_logic                                         -- clk
        );
    end component clocky;
begin
    u0 : component clocky
        port map (
            CLOCK_50,
            '1',
            DRAM_ADDR,
            DRAM_BA,
            DRAM_CAS_N,
            DRAM_CKE,
            DRAM_CS_N,
            DRAM_DQ,
            DRAM_DQM,
            DRAM_RAS_N,
            DRAM_WE_N,
            SDRAM_ADDR,
            SDRAM_BE_N,
            SDRAM_CS,
            SDRAM_WRITEDATA,
            SDRAM_RE_N,
            SDRAM_WE_N,
            SDRAM_READDATA,
            SDRAM_RDVAL,
            SDRAM_WAIT,
            clk143
        );

		  
DRAM_LDQM<=DRAM_DQM(0);
DRAM_UDQM<=DRAM_DQM(1);
DRAM_CLK<=clk143;
SDRAM_CS<='1';
SDRAM_BE_N<="00";		  
		  
PROCESS (CLK143)
variable cnt: integer range 0 to 100;
begin
if rising_edge(clk143)then

case BUFF_CTRL is
when st0=>    

if (SDRAM_WAIT='0') then
SDRAM_WE_N<='0';
SDRAM_RE_N<='1';
IF SDRAM_ADDR = "0000000000000000000000000" THEN
SDRAM_ADDR<="0000000000000000000000001";	
SDRAM_WRITEDATA(7 downto 0)<="10101010";
BUFF_CTRL<=st1;
END IF;
end if;



when st1=>

if (SDRAM_WAIT='0') then
SDRAM_WE_N<='1';
SDRAM_RE_N<='0';
SDRAM_ADDR<="0000000000000000000000000";
LED1<=SDRAM_READDATA(7 downto 0);
OUTPUT<=SDRAM_READDATA(7 downto 0);
BUFF_CTRL<=st2;

END IF;
when st2=>


when others=>NULL;
END CASE;

end if;
end process;
end main;