module gr(clk,rst,x,slot1);
 
 input clk,rst;

  input [95:0]x;
  
output reg [671:0]slot1;
 
 reg [7:0]slot [6:0] [11:0];

  integer i,j;

 reg [95:0]k,k1;
 
 always@(posedge clk)


  begin

    if(rst==1)

      begin

          k=x;

  i=0;
 
 j=0;

end
 
else

   begin

  if(i<=6)
  
  begin
   
   if(j<=11)
     
   begin
       
   k1=k-4'b1000;
    
    slot[i][j]=x[k:k1];
      
  j=j+1;
      
  k=k-9;
     
 end
      
i=i+1;
  
  end
 
 end
 
 end
endmodule