library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Frequency_Interleaver_v1_0 is generic ( -- Users to add parameters here C_S00_AXIS_TUSER_WIDTH : integer := 8; -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S00_AXI C_S00_AXI_DATA_WIDTH : integer := 32; C_S00_AXI_ADDR_WIDTH : integer := 9; -- Parameters of Axi Slave Bus Interface S00_AXIS C_S00_AXIS_TDATA_WIDTH : integer := 32; -- Parameters of Axi Master Bus Interface M00_AXIS C_M00_AXIS_TDATA_WIDTH : integer := 32; C_M00_AXIS_START_COUNT : integer := 32 ); port ( -- Users to add ports here s00_axis_tuser : in std_logic_vector(C_S00_AXIS_TUSER_WIDTH-1 downto 0); aclk : in std_logic; aresetn : in std_logic; -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S00_AXI -- s00_axi_aclk : in std_logic; -- s00_axi_aresetn : in std_logic; s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_awprot : in std_logic_vector(2 downto 0); s00_axi_awvalid : in std_logic; s00_axi_awready : out std_logic; s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); s00_axi_wvalid : in std_logic; s00_axi_wready : out std_logic; s00_axi_bresp : out std_logic_vector(1 downto 0); s00_axi_bvalid : out std_logic; s00_axi_bready : in std_logic; s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); s00_axi_arprot : in std_logic_vector(2 downto 0); s00_axi_arvalid : in std_logic; s00_axi_arready : out std_logic; s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); s00_axi_rresp : out std_logic_vector(1 downto 0); s00_axi_rvalid : out std_logic; s00_axi_rready : in std_logic; -- Ports of Axi Slave Bus Interface S00_AXIS -- s00_axis_aclk : in std_logic; -- s00_axis_aresetn : in std_logic; s00_axis_tready : out std_logic; s00_axis_tdata : in std_logic_vector(C_S00_AXIS_TDATA_WIDTH-1 downto 0); s00_axis_tstrb : in std_logic_vector((C_S00_AXIS_TDATA_WIDTH/8)-1 downto 0); s00_axis_tlast : in std_logic; s00_axis_tvalid : in std_logic; -- Ports of Axi Master Bus Interface M00_AXIS -- m00_axis_aclk : in std_logic; -- m00_axis_aresetn : in std_logic; m00_axis_tvalid : out std_logic; m00_axis_tdata : out std_logic_vector(C_M00_AXIS_TDATA_WIDTH-1 downto 0); m00_axis_tstrb : out std_logic_vector((C_M00_AXIS_TDATA_WIDTH/8)-1 downto 0); m00_axis_tlast : out std_logic; m00_axis_tready : in std_logic ); end Frequency_Interleaver_v1_0; architecture arch_imp of Frequency_Interleaver_v1_0 is -- function called clogb2 that returns an integer which has the -- value of the ceiling of the log base 2. function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; begin if (depth = 0) then return(0); else for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if(depth <= 1) then return(clogb2); else depth := depth / 2; end if; end loop; return(0); end if; end; -- component declaration component Frequency_Interleaver_v1_0_S00_AXI is generic ( C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 7 ); port ( SLV_REG_0 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_1 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_2 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_3 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_4 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_5 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_6 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_7 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_8 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_9 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_10 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_11 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_12 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_13 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_14 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_15 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_16 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_17 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_18 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_19 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_20 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_21 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_22 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_23 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_24 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_25 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_26 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_27 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_28 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_29 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_30 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_31 : in std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_32 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_33 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_34 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_35 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_36 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_37 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_38 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_39 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_40 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_41 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_42 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_43 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_44 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_45 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_46 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_47 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_48 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_49 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_50 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_51 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_52 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_53 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_54 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_55 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_56 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_57 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_58 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_59 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_60 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_61 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_62 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_63 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_64 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_65 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_66 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_67 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_68 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_69 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_70 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_71 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_72 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_73 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_74 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_75 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_76 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_77 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_78 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_79 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_80 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_81 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_82 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_83 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_84 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_85 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_86 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_87 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_88 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_89 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_90 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_91 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_92 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_93 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_94 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); SLV_REG_95 : out std_logic_vector( C_S_AXI_DATA_WIDTH-1 downto 0 ); S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic ); end component Frequency_Interleaver_v1_0_S00_AXI; constant MAX_BITS_PER_CARRIER : integer := 6; constant MAX_VALUES_PER_CARRIER : integer := 2**MAX_BITS_PER_CARRIER; constant MAX_BITS_PER_CARRIER_BITS : integer := clogb2(MAX_BITS_PER_CARRIER); constant MAX_CARRIERS : integer := 2048; constant MAX_CARRIERS_BITS : integer := clogb2(MAX_CARRIERS); constant MAX_BITS_PER_SYMBOL : integer := MAX_BITS_PER_CARRIER * MAX_CARRIERS; constant MAX_BITS_PER_SYMBOL_BITS : integer := clogb2(MAX_BITS_PER_SYMBOL); constant FFT_RESOLUTION_BITS : integer := 16; constant MAX_DWORDS_PER_SYMBOL : integer := MAX_BITS_PER_SYMBOL / 32; type PING_PONG_BIT_BUFFER is array (1 downto 0) of std_logic_vector(MAX_BITS_PER_SYMBOL-1 downto 0); type MODULATION_LUT is array (MAX_VALUES_PER_CARRIER-1 downto 0) of std_logic_vector(2 * FFT_RESOLUTION_BITS - 1 downto 0); signal rx_bit_buf_sel : integer range 0 to 1; signal tx_bit_buf_sel : integer range 0 to 1; signal tx_bit_buf_ofs : integer range 0 to MAX_BITS_PER_SYMBOL; signal rx_bit_buf_ofs : integer range 0 to MAX_BITS_PER_SYMBOL; -- signal bit_buffer : PING_PONG_BIT_BUFFER; signal bit_buffer : std_logic_vector(2*MAX_BITS_PER_SYMBOL-1 downto 0); signal modulation_table : MODULATION_LUT; signal rx_symbol_done : std_logic; signal rx_symbol_rdy : std_logic; signal tx_symbol_done : std_logic; constant MAX_N : integer := MAX_CARRIERS; constant MAX_N_BITS : integer := clogb2(MAX_N); constant MAX_N_SHFT_BITS : integer := clogb2(MAX_N_BITS-1); constant MAX_K : integer := 64; constant MAX_K_BITS : integer := clogb2(MAX_K); constant MAX_K_SHFT_BITS : integer := clogb2(MAX_K_BITS-1); constant MAX_M : integer := 128; constant MAX_M_BITS : integer := clogb2(MAX_M); constant MAX_M_SHFT_BITS : integer := clogb2(MAX_M_BITS-1); signal n_carriers : integer range 0 to MAX_CARRIERS; signal n_tx_symbol_bits : integer range 0 to MAX_BITS_PER_SYMBOL; signal n_rx_symbol_bits : integer range 0 to MAX_BITS_PER_SYMBOL; signal n_padding_bits : integer range 0 to 32; signal n_carrier_bits : integer range 0 to MAX_BITS_PER_CARRIER; signal N_shft : integer range 0 to MAX_N_BITS-1; signal K_shft : integer range 0 to MAX_K_BITS-1; signal K_mask : std_logic_vector(MAX_N_BITS-1 downto 0); signal M_shft : integer range 0 to MAX_M_BITS-1; signal axis_in_tready : std_logic; signal axis_in_tvalid : std_logic; signal axis_in_tuser : std_logic_vector(C_S00_AXIS_TUSER_WIDTH-1 downto 0); signal axis_in_tdata : std_logic_vector(C_S00_AXIS_TDATA_WIDTH-1 downto 0); signal axis_out_tready : std_logic; signal axis_out_tvalid : std_logic; signal axis_out_tdata : std_logic_vector(C_M00_AXIS_TDATA_WIDTH-1 downto 0); signal soft_reset : std_logic; signal soft_start : std_logic; signal ctrl_reg_in : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal tx_carrier_idx : integer range 0 to MAX_CARRIERS; signal rx_bit_buf_ptr : integer range 0 to MAX_BITS_PER_SYMBOL; -- input registers from AXI lite port signal slv_reg_0 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_1 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_2 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_3 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_4 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_5 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_6 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_7 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_8 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_9 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_10 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_11 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_12 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_13 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_14 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_15 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); -- output registers to AXI lite port signal slv_reg_16 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_17 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_18 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_19 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_20 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_21 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_22 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_23 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_24 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_25 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_26 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_27 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_28 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_29 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_30 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_31 : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); begin -- Instantiation of Axi Bus Interface S00_AXI Frequency_Interleaver_v1_0_S00_AXI_inst : Frequency_Interleaver_v1_0_S00_AXI generic map ( C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH ) port map ( SLV_REG_0 => slv_reg_0, SLV_REG_1 => slv_reg_1, SLV_REG_2 => slv_reg_2, SLV_REG_3 => slv_reg_3, SLV_REG_4 => slv_reg_4, SLV_REG_5 => slv_reg_5, SLV_REG_6 => slv_reg_6, SLV_REG_7 => slv_reg_7, SLV_REG_8 => slv_reg_8, SLV_REG_9 => slv_reg_9, SLV_REG_10 => slv_reg_10, SLV_REG_11 => slv_reg_11, SLV_REG_12 => slv_reg_12, SLV_REG_13 => slv_reg_13, SLV_REG_14 => slv_reg_14, SLV_REG_15 => slv_reg_15, SLV_REG_16 => slv_reg_16, SLV_REG_17 => slv_reg_17, SLV_REG_18 => slv_reg_18, SLV_REG_19 => slv_reg_19, SLV_REG_20 => slv_reg_20, SLV_REG_21 => slv_reg_21, SLV_REG_22 => slv_reg_22, SLV_REG_23 => slv_reg_23, SLV_REG_24 => slv_reg_24, SLV_REG_25 => slv_reg_25, SLV_REG_26 => slv_reg_26, SLV_REG_27 => slv_reg_27, SLV_REG_28 => slv_reg_28, SLV_REG_29 => slv_reg_29, SLV_REG_30 => slv_reg_30, SLV_REG_31 => slv_reg_31, SLV_REG_32 => modulation_table(0 ), SLV_REG_33 => modulation_table(1 ), SLV_REG_34 => modulation_table(2 ), SLV_REG_35 => modulation_table(3 ), SLV_REG_36 => modulation_table(4 ), SLV_REG_37 => modulation_table(5 ), SLV_REG_38 => modulation_table(6 ), SLV_REG_39 => modulation_table(7 ), SLV_REG_40 => modulation_table(8 ), SLV_REG_41 => modulation_table(9 ), SLV_REG_42 => modulation_table(10), SLV_REG_43 => modulation_table(11), SLV_REG_44 => modulation_table(12), SLV_REG_45 => modulation_table(13), SLV_REG_46 => modulation_table(14), SLV_REG_47 => modulation_table(15), SLV_REG_48 => modulation_table(16), SLV_REG_49 => modulation_table(17), SLV_REG_50 => modulation_table(18), SLV_REG_51 => modulation_table(19), SLV_REG_52 => modulation_table(20), SLV_REG_53 => modulation_table(21), SLV_REG_54 => modulation_table(22), SLV_REG_55 => modulation_table(23), SLV_REG_56 => modulation_table(24), SLV_REG_57 => modulation_table(25), SLV_REG_58 => modulation_table(26), SLV_REG_59 => modulation_table(27), SLV_REG_60 => modulation_table(28), SLV_REG_61 => modulation_table(29), SLV_REG_62 => modulation_table(30), SLV_REG_63 => modulation_table(31), SLV_REG_64 => modulation_table(32), SLV_REG_65 => modulation_table(33), SLV_REG_66 => modulation_table(34), SLV_REG_67 => modulation_table(35), SLV_REG_68 => modulation_table(36), SLV_REG_69 => modulation_table(37), SLV_REG_70 => modulation_table(38), SLV_REG_71 => modulation_table(39), SLV_REG_72 => modulation_table(40), SLV_REG_73 => modulation_table(41), SLV_REG_74 => modulation_table(42), SLV_REG_75 => modulation_table(43), SLV_REG_76 => modulation_table(44), SLV_REG_77 => modulation_table(45), SLV_REG_78 => modulation_table(46), SLV_REG_79 => modulation_table(47), SLV_REG_80 => modulation_table(48), SLV_REG_81 => modulation_table(49), SLV_REG_82 => modulation_table(50), SLV_REG_83 => modulation_table(51), SLV_REG_84 => modulation_table(52), SLV_REG_85 => modulation_table(53), SLV_REG_86 => modulation_table(54), SLV_REG_87 => modulation_table(55), SLV_REG_88 => modulation_table(56), SLV_REG_89 => modulation_table(57), SLV_REG_90 => modulation_table(58), SLV_REG_91 => modulation_table(59), SLV_REG_92 => modulation_table(60), SLV_REG_93 => modulation_table(61), SLV_REG_94 => modulation_table(62), SLV_REG_95 => modulation_table(63), S_AXI_ACLK => aclk, S_AXI_ARESETN => aresetn, S_AXI_AWADDR => s00_axi_awaddr, S_AXI_AWPROT => s00_axi_awprot, S_AXI_AWVALID => s00_axi_awvalid, S_AXI_AWREADY => s00_axi_awready, S_AXI_WDATA => s00_axi_wdata, S_AXI_WSTRB => s00_axi_wstrb, S_AXI_WVALID => s00_axi_wvalid, S_AXI_WREADY => s00_axi_wready, S_AXI_BRESP => s00_axi_bresp, S_AXI_BVALID => s00_axi_bvalid, S_AXI_BREADY => s00_axi_bready, S_AXI_ARADDR => s00_axi_araddr, S_AXI_ARPROT => s00_axi_arprot, S_AXI_ARVALID => s00_axi_arvalid, S_AXI_ARREADY => s00_axi_arready, S_AXI_RDATA => s00_axi_rdata, S_AXI_RRESP => s00_axi_rresp, S_AXI_RVALID => s00_axi_rvalid, S_AXI_RREADY => s00_axi_rready ); -- Add user logic here s00_axis_tready <= axis_in_tready; axis_in_tvalid <= s00_axis_tvalid; axis_in_tuser <= s00_axis_tuser; axis_in_tdata <= s00_axis_tdata; axis_out_tready <= m00_axis_tready; m00_axis_tvalid <= axis_out_tvalid; m00_axis_tdata <= axis_out_tdata; -- receive process Receive_Symbol: process( aclk ) variable rx_bit_buf_ptr : integer range 0 to MAX_BITS_PER_SYMBOL; variable rx_bits : integer range 0 to 32; begin if rising_edge( aclk ) then if (aresetn = '0') then rx_symbol_done <= '0'; tx_bit_buf_sel <= 0; rx_bit_buf_sel <= 1; tx_bit_buf_ofs <= MAX_BITS_PER_SYMBOL; rx_bit_buf_ptr := 0; axis_in_tready <= '0'; elsif (soft_reset = '1') then rx_symbol_done <= '0'; tx_bit_buf_sel <= 0; rx_bit_buf_sel <= 1; tx_bit_buf_ofs <= MAX_BITS_PER_SYMBOL; rx_bit_buf_ptr := 0; axis_in_tready <= '0'; elsif (soft_start = '1') then n_carriers <= to_integer(unsigned(slv_reg_1(MAX_CARRIERS_BITS downto 0))); n_rx_symbol_bits <= to_integer(unsigned(slv_reg_2(MAX_BITS_PER_SYMBOL_BITS downto 0))); n_tx_symbol_bits <= to_integer(unsigned(slv_reg_3(MAX_BITS_PER_SYMBOL_BITS downto 0))); n_padding_bits <= n_tx_symbol_bits - n_rx_symbol_bits; n_carrier_bits <= to_integer(unsigned(slv_reg_4(MAX_BITS_PER_CARRIER_BITS downto 0))); N_shft <= to_integer(unsigned(slv_reg_5(MAX_N_SHFT_BITS downto 0))); K_shft <= to_integer(unsigned(slv_reg_6(MAX_K_SHFT_BITS downto 0))); K_mask <= slv_reg_7(MAX_N_BITS-1 downto 0); M_shft <= to_integer(unsigned(slv_reg_8(MAX_M_SHFT_BITS downto 0))); rx_symbol_done <= '0'; rx_bit_buf_sel <= 0; tx_bit_buf_sel <= 1; tx_bit_buf_ofs <= MAX_BITS_PER_SYMBOL; rx_bit_buf_ptr := 0; axis_in_tready <= '1'; else if ((axis_in_tvalid and axis_in_tready) = '1') then --non static ranges prohibited by Vivado -- bit_buffer(rx_bit_buf_ptr to rx_bit_buf_ptr + rx_bits - 1) <= axis_in_tdata(0 to rx_bits - 1); rx_bits := to_integer(unsigned(axis_in_tuser)); for i in 1 to 32 loop bit_buffer(rx_bit_buf_ptr) <= axis_in_tdata(i-1); rx_bit_buf_ptr := rx_bit_buf_ptr + 1; if i = rx_bits then exit; end if; end loop; if (rx_bit_buf_ptr - rx_bit_buf_ofs = n_rx_symbol_bits) then -- a symbol's worth of bits may not fit exactly -- for i in 0 to 32 loop -- if i = n_padding_bits then -- exit; -- else -- bit_buffer(rx_bit_buf_sel)(rx_bit_buf_ptr) <= '0'; -- rx_bit_buf_ptr := rx_bit_buf_ptr + 1; -- end if; -- end loop; rx_symbol_done <= '1'; axis_in_tready <= '0'; else rx_symbol_done <= '0'; axis_in_tready <= '1'; end if; end if; if (( rx_symbol_done and tx_symbol_done ) = '1') then rx_symbol_done <= '0'; rx_bit_buf_sel <= tx_bit_buf_sel; if (tx_bit_buf_sel = 1) then tx_bit_buf_sel <= 0; tx_bit_buf_ofs <= MAX_BITS_PER_SYMBOL; rx_bit_buf_ptr := 0; else tx_bit_buf_sel <= 1; tx_bit_buf_ofs <= 0; rx_bit_buf_ptr := MAX_BITS_PER_SYMBOL; end if; axis_in_tready <= '1'; end if; end if; end if; end process; -- transmit process Transmit_Symbol: process( aclk ) variable bits_out : std_logic_vector(MAX_BITS_PER_CARRIER-1 downto 0); variable idx_n_slv : std_logic_vector(MAX_CARRIERS_BITS-1 downto 0); variable idx_b_slv : std_logic_vector(MAX_BITS_PER_CARRIER-1 downto 0); begin if rising_edge( aclk ) then if (aresetn = '0') then bits_out := ( others => '0' ); idx_n_slv := ( others => '0' ); idx_b_slv := ( others => '0' ); tx_symbol_done <= '1'; axis_out_tvalid <= '0'; tx_carrier_idx <= 0; elsif (soft_reset = '1') then bits_out := ( others => '0' ); idx_n_slv := ( others => '0' ); idx_b_slv := ( others => '0' ); tx_symbol_done <= '1'; axis_out_tvalid <= '0'; tx_carrier_idx <= 0; elsif (soft_start = '1') then null; else if (( tx_symbol_done = '0' ) and (( axis_out_tvalid = '0' ) or (( axis_out_tvalid and axis_out_tready ) = '1'))) then -- obtain interleaved bit pattern if ( tx_carrier_idx = n_carriers ) then tx_symbol_done <= '1'; axis_out_tvalid <= '0'; else bits_out := ( others => '0' ); idx_n_slv := std_logic_vector(to_unsigned(tx_carrier_idx, idx_n_slv'length)); case n_carrier_bits is when 2 => for idx_b in 0 to 1 loop idx_b_slv := std_logic_vector(to_unsigned(idx_b, idx_b_slv'length)); bits_out(idx_b) := bit_buffer( ( to_integer(shift_right(unsigned(idx_n_slv), K_shft ))) + ( to_integer( shift_left(unsigned(idx_n_slv and K_mask), M_shft ))) + ( to_integer( shift_left(unsigned(idx_b_slv), N_shft ))) + tx_bit_buf_ofs ); end loop; when 4 => for idx_b in 0 to 3 loop idx_b_slv := std_logic_vector(to_unsigned(idx_b, idx_b_slv'length)); bits_out(idx_b) := bit_buffer( ( to_integer(shift_right(unsigned(idx_n_slv), K_shft ))) + ( to_integer( shift_left(unsigned(idx_n_slv and K_mask), M_shft ))) + ( to_integer( shift_left(unsigned(idx_b_slv), N_shft ))) + tx_bit_buf_ofs ); end loop; when 6 => for idx_b in 0 to 5 loop idx_b_slv := std_logic_vector(to_unsigned(idx_b, idx_b_slv'length)); bits_out(idx_b) := bit_buffer( ( to_integer(shift_right(unsigned(idx_n_slv), K_shft ))) + ( to_integer( shift_left(unsigned(idx_n_slv and K_mask), M_shft ))) + ( to_integer( shift_left(unsigned(idx_b_slv), N_shft ))) + tx_bit_buf_ofs ); end loop; when others => null; end case; tx_carrier_idx <= tx_carrier_idx + 1; axis_out_tdata <= modulation_table(to_integer(unsigned(bits_out))); axis_out_tvalid <= '1'; end if; end if; if (( rx_symbol_done and tx_symbol_done ) = '1') then -- start transmission of next symbol tx_symbol_done <= '0'; tx_carrier_idx <= 0; axis_out_tvalid <= '0'; end if; end if; end if; end process; --control register process: Control_Register: process( aclk ) begin if rising_edge( aclk ) then if (aresetn = '0') then soft_reset <= '0'; soft_start <= '0'; ctrl_reg_in <= (others=>'0'); else soft_reset <= '0'; soft_start <= '0'; ctrl_reg_in <= slv_reg_0; if (ctrl_reg_in = x"5AA50FF0" and slv_reg_0 = x"00000000") then soft_reset <= '1'; elsif (ctrl_reg_in = x"A55AF00F" and slv_reg_0 = x"00000000") then soft_start <= '1'; end if; end if; end if; end process; -- User logic ends end arch_imp;