module test_ENCODER ; reg [7:0] ENC_IN; reg ENC_CLK,ENC_RST,KI; wire [9:0] ENC_OUT; integer i; ENCODER e0(.ENC_OUT(ENC_OUT),.ENC_CLK(ENC_CLK),.ENC_RST(ENC_RST),.KI(KI),.ENC_IN(ENC_IN)); initial begin ENC_IN<=8'b00010101; KI<=1'b0; ENC_RST<=1'b0; ENC_CLK<=1'b1; end always #5 ENC_CLK=!ENC_CLK; initial begin for(i=0;i<32;i=i+1) begin #10; ENC_RST<=1'b1; KI<=1'b0; ENC_IN<=ENC_IN+i; end #20 $stop; end endmodule