library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity iir_tb is end entity iir_tb; architecture testbench of iir_tb is constant tb_clk_period : time := 1 sec / 100_000_000; signal tb_signal_period : time := 1 sec / 100_000; signal simulation_run : boolean := true; signal tb_clk : std_logic := '0'; signal tb_clk_adc : std_logic; signal tb_clk_dac : std_logic; signal tb_adc_data : std_logic_vector(9 downto 0) := (others => '0'); signal tb_dac_data : std_logic_vector(9 downto 0); begin tb_clk <= not tb_clk after tb_clk_period / 2 when simulation_run; process begin tb_adc_data <= std_logic_vector( to_signed( -500, tb_adc_data'length)); wait for tb_signal_period / 2; tb_adc_data <= std_logic_vector( to_signed( 500, tb_adc_data'length)); wait for tb_signal_period / 2; if ( not simulation_run) or ( tb_signal_period < tb_clk_period) then simulation_run <= false; wait; -- forever else tb_signal_period <= tb_signal_period / 1.01; end if; end process; dut: entity work.dsp port map ( clk => tb_clk, -- : in std_logic := '0'; clk_adc => tb_clk_adc, -- : out std_logic := '0'; clk_dac => tb_clk_dac, -- : out std_logic := '0'; adc_data => tb_adc_data, -- : in std_logic_vector(9 downto 0) := (others => '0'); dac_data => tb_dac_data -- : out std_logic_vector(9 downto 0) := (others => '0') ); end architecture testbench;