library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FreqDivider400Hz is port( clock : in STD_LOGIC; -- 50 Mhz clear : in STD_LOGIC; freq2 : out STD_LOGIC ); end FreqDivider400Hz; architecture Behavioral of FreqDivider400Hz is signal adjfreq: STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000"; signal adjclock : std_logic := '0'; begin freq2 <= adjclock; countClock: process(clock,clear) begin if (clear = '1') then adjfreq <= "0000000000000000"; elsif(clock'event and clock = '1') then -- Flip a the output once every 62500 cycles -- to give a 400Hz output with 50% duty cycle if (adjfreq = "1111010000100100") then adjfreq <= "0000000000000000"; if adjclock <= '0' then adjclock <= '1'; else adjclock <= '0'; end if; else adjfreq <= adjfreq+1; end if; end if; end process; end Behavioral;