library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FreqDivider is port( clock : in STD_LOGIC; -- 50 Mhz clear : in STD_LOGIC; adjclk : out STD_LOGIC ); end FreqDivider; architecture Behavioral of FreqDivider is signal adjfreq: STD_LOGIC_VECTOR(17 downto 0) := "000000000000000000"; signal adjcntr: STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); signal adjclock : std_logic := '0'; begin adjclk <= adjclock; countClock: process(clock,clear,adjfreq) begin if (clear = '1') then adjfreq <= "000000000000000000"; elsif(clock'event and clock = '1') then if (adjfreq = "111101000010010000") then --50MHz/250000=200Hz adjfreq <= "000000000000000000"; adjclock <= '1'; else adjfreq <= adjfreq+1; adjclock <= '0'; end if; end if; end process; process(adjclock) begin if (adjclock 'event and adjclock ='1') then if adjcntr = "101" then adjcntr <= "000"; else adjcntr <= adjcntr+1; end if; end if; end process; end Behavioral;