library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity cla_nbits is generic (N : integer := 8); Port ( a : in STD_LOGIC_VECTOR (N-1 downto 0); b : in STD_LOGIC_VECTOR (N-1 downto 0); cin : in STD_LOGIC; sum : out STD_LOGIC_VECTOR (N-1 downto 0); cout : out STD_LOGIC); --inc : out STD_LOGIC_VECTOR (1 downto 0)); end cla_nbits; architecture Behavioral of cla_nbits is signal g : STD_LOGIC_VECTOR (N-1 downto 0); signal p : STD_LOGIC_VECTOR (N-1 downto 0); signal c : STD_LOGIC_VECTOR (N-1 downto 0); begin g <= a and b; p <= a xor b; --c(0) <= cin; p1: process(p,g,c,cin) begin c(0) <= cin; c(1) <= g(0) or (p(0) and cin); for i in 1 to N-2 loop c(i+1) <= g(i) or (p(i) and c(i)); end loop; cout <= g(N-1) or (p(N-1) and c(N-1)); end process; --inc(0) <= c(N/2); --inc(1) <= c(3*(N/4)); sum <= p xor c; end Behavioral;