library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity add_ctrl is port ( clk : in STD_LOGIC; res : in STD_LOGIC; selA, selB, mux_ctrl : out STD_LOGIC); end add_ctrl; architecture Behavioral of add_ctrl is type state_type is (IDLE, ADD_LOW, ADD_HIGH); signal state, next_state : state_type; signal selA_sig, selB_sig, mux_sel_sig : STD_LOGIC; begin state_r: process (clk, res) begin if (res = '1') then state <= IDLE; elsif clk'event and clk = '1' then state <= next_state; end if; end process state_r; decision: process (state) begin case state is when IDLE => next_state <= ADD_LOW; when ADD_LOW => selA <= '0'; selB <= '0'; mux_ctrl <= '0'; next_state <= ADD_HIGH; when ADD_HIGH => selA <= '1'; selB <= '1'; mux_ctrl <= '1'; next_state <= IDLE; end case; end process; end Behavioral;