LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lattice; USE lattice.components.all; library IEEE; --USE ieee.numeric_std.ALL; use ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; ENTITY blinking_led IS PORT( clk,data : in std_logic; A_In : in std_logic; B_In : in std_logic; Reset : in std_logic; CSpin,clk_out : out bit; data_out : out std_logic_vector(11 downto 0)); END blinking_led; ARCHITECTURE behavior OF blinking_led IS signal temporal: bit := '0' ; signal enable: bit := '0' ; signal stop: bit := '0' ; signal start: bit := '0' ; signal flow: integer range 0 to 3 := 0 ; signal Chipselect: bit :='1'; signal spiposition: std_logic_vector(15 downto 0); signal count1: std_logic_vector(11 downto 0):="000000000000"; signal count2: std_logic_vector(11 downto 0):="000000000000"; signal count3: std_logic_vector(11 downto 0):="000000000000"; -- signal flow : INTEGER RANGE 0 TO 3; signal counter : INTEGER RANGE 0 TO 10170; SIGNAL Last_A, Last_B :std_logic; SIGNAL Current_A, Current_B : std_logic; SIGNAL Dir : std_logic; SIGNAL up_down : std_logic; begin up_down <= Current_A xor Last_A xor Current_B xor Last_B; Dir <= CURRENT_A xor Last_B; PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(counter < 10170) THEN counter <= counter + 1; ELSE counter <= 0; END IF; end if; END PROCESS; time_case: process (counter,data,spiposition,temporal,clk,flow,reset,dir,up_down,chipselect) begin case flow is when 0 => case counter is when 10000 => Chipselect<='0'; when 10020 => temporal <='1'; when 10024 => temporal <='0'; spiposition(15)<= data; when 10028 => temporal <='1'; when 10032 => temporal <='0'; spiposition(14)<= data; when 10036 => temporal <='1'; when 10040 => temporal <='0'; spiposition(13)<= data; when 10044 => temporal <='1'; when 10048 => temporal <='0'; spiposition(12)<= data; when 10052 => temporal <='1'; when 10056 => temporal <='0'; spiposition(11)<= data; when 10060 => temporal <='1'; when 10064 => temporal <='0'; spiposition(10)<= data; when 10068 => temporal <='1'; when 10072 => temporal <='0'; spiposition(9)<= data; when 10076 => temporal <='1'; when 10080 => temporal <='0'; spiposition(8)<= data; when 10084 => temporal <='1'; when 10088 => temporal <='0'; spiposition(7)<= data; when 10092 => temporal <='1'; when 10096 => temporal <='0'; spiposition(6)<= data; when 10100 => temporal <='1'; when 10104 => temporal <='0'; spiposition(5)<= data; when 10108 => temporal <='1'; when 10112 => temporal <='0'; spiposition(4)<= data; when 10116 => temporal <='1'; when 10120 => temporal <='0'; spiposition(3)<= data; when 10124 => temporal <='1'; when 10128 => temporal <='0'; spiposition(2)<= data; when 10132 => temporal <='1'; when 10136 => temporal <='0'; spiposition(1)<= data; when 10140 => temporal <='1'; when 10144 => temporal <='0'; spiposition(0)<= data; when 10152 => Chipselect<='1'; when 10156 => count1<= spiposition(13 downto 2); when 10168 =>flow<=1; when others=>null; end case; when 1 => if rising_edge(clk) then count2<=count1; flow<=2; end if; when 2 => IF (Reset = '1') THEN count2 <= "000000000000"; ELSIF (clk'EVENT AND clk= '1') THEN if up_down ='1' then if(dir='1') then count2<=count2+1; else count2<=count2-1; end if; end if; end if; when others=>null; end case; end process; process (clk, Reset,flow) begin if Reset = '1' then Last_A <= '0'; Last_B <= '0'; Current_A <= '0'; Current_B <= '0'; elsif rising_edge(clk) then Last_A <= Current_A; Last_B <= Current_B; Current_A <= A_In; Current_B <= B_In; end if; end process; data_out<=count2(11 downto 0); CSpin<=Chipselect; clk_out<=temporal; END behavior;