//`define TEST 1 module TX( input clk, input reset, input transmit, output reg EN, //output reg ER, output reg [3:0] TX, output reg [3:0] state, //crc test outputs output [3:0] crc_out, output init_crc, output crc_rd, output crc_en ); parameter IDLE = 2'd0; parameter PREAMBLE = 2'd1; parameter MAC_DEST = 2'd2; parameter MAC_SOUR = 2'd3; parameter LENGTH = 3'd4; parameter DATA = 3'd5; parameter CRC = 3'd6; parameter GAP = 3'd7; parameter WAIT = 4'd8; parameter TEST =1'b0; parameter TESTS=1'b1; parameter TESTCRC=1'b1; //reg [2:0] state; reg [7:0] cnt; reg [7:0] MACD; /* temporary, for test outputs wire init_crc; wire crc_rd; wire crc_en; */ wire [31:0] crc32; wire [3:0]crc_out; //assign crc_probe = crc_out; assign crc_rd = (state == CRC); assign crc_en = ( (state == MAC_DEST) || (state == MAC_SOUR) || (state == LENGTH) || (state == DATA) ); assign init_crc = (state == IDLE); //cpu mac 00:23:7D:2C:0C:97 //bits are transmitted from least sig to most sig // Transmit state machine always @ (posedge clk or posedge reset) begin if (reset) begin //crc_en <= 1'b0; state <= IDLE; TX[3:0] <= 4'b0000; end else begin case (state) IDLE: begin EN <= 1'b0; TX[3:0] <= 4'b0000; cnt <= 4'd15; //for 7 preamble octets 0x55 + first 4b of SFD (0x5) state <= PREAMBLE; end PREAMBLE: begin EN <= 1'b1; if (cnt > 1) begin cnt <= cnt -1; TX[3:0] <= 4'b0101; state <= PREAMBLE; end else if (cnt == 1) begin cnt <= cnt -1; TX[3:0]<=4'b1101; //second 4b of SFD (0xD) end else begin TX[3:0] <= 4'b0101; cnt <= 4'd11; MACD <= 8'd0; state <= MAC_DEST; end end MAC_DEST: begin EN <= 1'b1; if (cnt > 0) begin cnt <= cnt -1; if ( TEST == 1) begin case (MACD) 0: begin TX[3:0] <= 4'b0000; MACD <= 8'd1; end 1: begin TX[3:0] <= 4'b0000; MACD <= 8'd2; end 2: begin TX[3:0] <= 4'b1100; // h23 reversed 1st part 0010 0011 -> 1100 0100 MACD <= 8'd3; end 3: begin TX[3:0] <= 4'b0100; //2nd part MACD <= 8'd4; end 4: begin TX[3:0] <= 4'b1011; //h7d 0111 1101 MACD <= 8'd5; end 5: begin TX[3:0] <= 4'b1110; MACD <= 8'd6; end 6: begin TX[3:0] <= 4'b0011; //h2c 0010 1100 MACD <= 8'd7; end 7: begin TX[3:0] <= 4'b0100; MACD <= 8'd8; end 8: begin TX[3:0] <= 4'b0011; //h0C 0000 1100 MACD <= 8'd9; end 9: begin TX[3:0] <= 4'b0000; MACD <= 8'd10; end 10: begin TX[3:0] <= 4'b1110; //h97 1001 0111 MACD <= 8'd11; end 11: begin TX[3:0] <= 4'b1001; MACD <= 8'd12; end default: begin end endcase end else begin TX[3:0] <= 4'b1111; end state <= MAC_DEST; end else begin if (TEST==1) begin TX[3:0] <= 4'b1001; // end MACD <= 8'd0; cnt <= 4'd11; state <= MAC_SOUR; end end MAC_SOUR: begin EN <= 1'b1; if (cnt > 0) begin cnt <= cnt -1; if ( TESTS == 1) begin case (MACD) 0: begin TX[3:0] <= 4'b0000; MACD <= 8'd1; end 1: begin TX[3:0] <= 4'b0000; MACD <= 8'd2; end 2: begin TX[3:0] <= 4'b1000; // MACD <= 8'd3; end 3: begin TX[3:0] <= 4'b1000; // MACD <= 8'd4; end 4: begin TX[3:0] <= 4'b0100; // MACD <= 8'd5; end 5: begin TX[3:0] <= 4'b0100; MACD <= 8'd6; end 6: begin TX[3:0] <= 4'b1100; // MACD <= 8'd7; end 7: begin TX[3:0] <= 4'b1100; MACD <= 8'd8; end 8: begin TX[3:0] <= 4'b0010; // MACD <= 8'd9; end 9: begin TX[3:0] <= 4'b0010; MACD <= 8'd10; end 10: begin TX[3:0] <= 4'b1010; // MACD <= 8'd11; end 11: begin TX[3:0] <= 4'b1010; MACD <= 8'd12; end default: begin end endcase end else begin TX[3:0] <= 4'b0000; end state <= MAC_SOUR; end else begin if (TESTS==1) begin TX[3:0] <= 4'b1010; // end cnt <= 4'd3; state <= LENGTH; end end LENGTH: begin EN <= 1'b1; if (cnt > 1) begin cnt <= cnt -1; TX[3:0] <= 4'b0000; state <= LENGTH; end else if (cnt == 1) begin cnt <= cnt -1; TX[3:0] <= 4'b0010; state <= LENGTH; end else begin TX[3:0] <= 4'b0110; cnt <= 8'd199; state <=DATA; end end DATA: begin EN <= 1'b1; if (cnt > 0) begin cnt <= cnt -1; TX[3:0] <= 4'b0000; state <= DATA; end else begin cnt <= 8'd7; MACD <= 8'd0; state <= CRC; end end CRC: begin EN <= 1'b1; if (cnt > 0) begin cnt <= cnt -1; if ( TESTCRC == 1) begin case (MACD) 0: begin TX[3:0] <= 4'b0011; MACD <= 8'd1; end 1: begin TX[3:0] <= 4'b1101; MACD <= 8'd2; end 2: begin TX[3:0] <= 4'b0100; // MACD <= 8'd3; end 3: begin TX[3:0] <= 4'b1011; // MACD <= 8'd4; end 4: begin TX[3:0] <= 4'b0001; // MACD <= 8'd5; end 5: begin TX[3:0] <= 4'b1111; MACD <= 8'd6; end 6: begin TX[3:0] <= 4'b0010; // MACD <= 8'd7; end default: begin end endcase end else begin TX[3:0] <= crc_out[3:0]; end state <= CRC; end else begin if (TESTCRC==1) begin TX[3:0] <= 4'b0010; // end else begin TX[3:0] <= crc_out[3:0]; end cnt <= 8'd23; state <= GAP; end end GAP: begin EN <= 1'b0; if (cnt ==4'd20) begin cnt <= cnt -1; end else if (cnt > 0) begin EN <= 1'b0; cnt <= cnt -1; TX[3:0] <= 4'b0000; state <= GAP; end else begin EN <= 1'b0; TX[3:0] <= 4'b0000; cnt <= 8'd199; state <= WAIT; // end end WAIT: begin EN <= 1'b0; if (cnt > 0) begin cnt <= cnt -1; TX[3:0] <= 4'b0000; state <= WAIT; end else begin state <= IDLE; end end endcase end //else end //always endmodule