library ieee; use ieee.std_logic_1164.all entity and is port(i1,i2: in std_logic; f1: out std_logic); end entity and; architecture and_beh of and is begin f1<= i1 and i2; end architecture and_beh; library ieee; use ieee.std_logic_1164.all entity or is port(i1,i2: in std_logic; f2: out std_logic); end entity or; architecture or_beh of or is begin f2<= i1 or i2; end architecture or_beh; library ieee; use ieee.std_logic_1164.all entity xor is port(i1,i2: in std_logic; f3: out std_logic); end entity xor; architecture xor_beh of xor is begin f3<= i1 xor i2; end architecture xor_beh; library ieee; use ieee.std_logic_1164.all entity not is port(i1: in std_logic; f4: out std_logic); end entity not; architecture not_beh of not is begin f4<= not i1; end architecture not_beh; library ieee; use ieee.std_logic_1164.all; entity strct is port(a,b: in std_logic; f: out std_logic); end entity strct; architecture strct_beh of strct is signal s1,s2,s3,s4: stf_logic; component and is port(i1,i2: in std_logic; f1: out std_logic); end component and; component or is port(i1,i2: in std_logic; f2: out std_logic); end component or; component xor is port(i1,i2: in std_logic; f3: out std_logic); end component xor; component not is port(i1: in std_logic; f4: out std_logic); end component not; begin M1: and port map(i1=>a,i2=>b,f1=>s1); M2: or port map(i1=>a,i2=>b,f2=>s2); M3: xor port map(i1=>a,i2=>b,f3=>s3); M4: not port map(i1=>a,f4=>s4); end architecture strct_beh; library ieee; use ieee.std_logic_1164.all entity mxer is port(s1,s2,s3,s4: in std_logic; sel: in std_logic_vector(1downto0); f5: out std_logic); end entity mxer; architecture mxer_beh of mxer is signal sel: std_logic; begin process(s1,s2,s3,s4,sel) begin if(sel="00")then f5<=s1; elsif(sel="01")then f5<=s2; elsif(sel="10")then f5<=s3; elsif(sel="11")then f5<=s4; end if; end process; end architecture mxer_beh;