`timescale 1ns/100ps module ENCODER(ENC_OUT,ENC_CLK, ENC_RST,KI, ENC_IN) ;//module name output [9:0]ENC_OUT; //Output port input ENC_CLK,ENC_RST,KI; //Input Port with control signal input [7:0]ENC_IN; // 8bit input port reg [9:0]ENC_OUT; // Internal wires adn regs wire ai,bi,ci,di,ei; reg fi,gi,hi,k; wire aeqb,ceqd,L22,L13,L31,L40,L04; wire PDL6,PDL4,NDL6; wire PD1S6,ND1S6,PD0S6,ND0S6; wire PD1S4,ND1S4,PD0S4,ND0S4; wire FNEG; reg S; reg LPDL6,LPDL4; wire COMPLS4,COMPLS6; wire SINT,NFO,NGO,NHO,NJO; wire NAO,NBO,NCO,NDO,NEO,NIO; //5b input function assign ai= ENC_IN[0]; assign bi= ENC_IN[1]; assign ci= ENC_IN[2]; assign di= ENC_IN[3]; assign ei= ENC_IN[4]; //3b input function always@(posedge ENC_CLK or negedge ENC_RST) begin if(!ENC_RST) begin fi<= 0; gi<= 0; hi<= 0; k<=0; end else begin fi<= ENC_IN[5]; gi<= ENC_IN[6]; hi<= ENC_IN[7]; k<=KI; end end assign aeqb= (ai & bi)|(!ai & !bi); assign ceqd= (ci & di)|(!ci & !di); assign L22 = (ai & bi & !ci & !di)|(ci & di & !ai & !bi)|(!aeqb & !ceqd);// 2 1's and 2 0's assign L13 = (!aeqb & !ci & !di)|(!ceqd & !ai & ! bi);//1 1's and 3 0's assign L31 = (!aeqb & ci & di)|(!ceqd & ai & bi); // 3 1's and 1 0's assign L40 = (ai & bi & ci & di); // all 1's assign L04 = (!ai & !bi & !ci & !di); //all 0's //Disparity Control assign PD1S6= (!L22 & !L31 & !ei)|(L13 & di & ei) ; assign ND1S6= (L31 & !di & !ei)|(ei & !L22 & !L13)|k; assign PD0S6= (!L22 & !L13 & ei)|k; assign ND0S6= PD1S6; assign FNEG= fi ^ gi; // creating S function always@(posedge ENC_CLK or negedge ENC_RST) begin if(!ENC_RST) S<=0; else S<=(PDL6 & L31 & di & !ei)|(NDL6 & L13 & ei & !di) ; end assign ND1S4 = (fi & gi); assign ND0S4 = (!fi & !gi); assign PD1S4 = (!fi & !gi) | (FNEG & k); assign PD0S4 = (fi & gi & hi); assign NDL6=!PDL6; assign PDL6=(PD0S6 & !COMPLS6)|(COMPLS6 & ND0S6)|(!ND0S6 & !PD0S6 & LPDL4); assign NDL6=!PDL6; assign PDL4=(LPDL6 & !PD0S4 & ! ND0S4)|(ND0S4 & COMPLS4)|(!COMPLS4 & PD0S4); //Disparity determine complementing S4 always@(posedge ENC_CLK or negedge ENC_RST) begin if(!ENC_RST) LPDL6<= 0; else LPDL6<=PDL6; end //Disparity determine complementing S6 always@(posedge ENC_CLK or negedge ENC_RST) begin if(!ENC_RST) LPDL4<=0; 59 else LPDL4<=~PDL4; end assign COMPLS4= (PD1S4 & !LPDL6) ^ (ND1S4 & LPDL6); assign COMPLS6= (ND1S6 & LPDL4) ^ (PD1S6 & !LPDL4); //5b/6b encoder // Logic for non-complemented Outputs assign NAO= ai; assign NBO= L04|(bi & !L40); assign NCO= ci | L04 | (L13 & di & ei); assign NDO= di & !L40; assign NEO= (ei & !(ei & di & L13))|(L13 & !ei); assign NIO= (L22 & !ei)|(ei & L04)|(ei & L40)|(k & L22)|(ei & !di & L13); always@(posedge ENC_CLK or negedge ENC_RST) begin if(!ENC_RST) ENC_OUT[5:0]<=6'b0; else begin ENC_OUT[0]<= COMPLS6 ^ NAO; ENC_OUT[1]<= COMPLS6 ^ NBO; ENC_OUT[2]<= COMPLS6 ^ NCO; ENC_OUT[3]<= COMPLS6 ^ NDO; ENC_OUT[4]<= COMPLS6 ^ NEO; ENC_OUT[5]<= COMPLS6 ^ NIO; end end //3B/4B encoder // Logic for non-complimented output assign SINT= (S & fi & gi & hi)|(k & fi & gi & hi); assign NFO= (fi & !SINT); assign NGO= gi | (!fi & !gi & !hi); assign NHO= hi; assign NJO= SINT|(FNEG & !hi); always@(posedge ENC_CLK or negedge ENC_RST) begin if(!ENC_RST) ENC_OUT[9:6]<=3'b0; else begin ENC_OUT[6]<= COMPLS4 ^ NFO; ENC_OUT[7]<= COMPLS4 ^ NGO; 60 ENC_OUT[8]<= COMPLS4 ^ NHO; ENC_OUT[9]<= COMPLS4 ^ NJO; end end endmodule