library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity ph_module is Port ( din : in STD_LOGIC_VECTOR (12 downto 0); r : in STD_LOGIC; c : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (25 downto 0)); end ph_module; architecture Behavioral of ph_module is signal sumsig : std_logic_vector ( 25 downto 0 ); signal sumsig1,sumsig2,sumsig3,sumsig4,sumsig5,sumsig6 : std_logic_vector ( 25 downto 0 ); signal commutator0,commutator1,commutator2,commutator3, commutator4,commutator5: std_logic_vector ( 12 downto 0 ); component subfilter1 port ( dins1 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts1 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter2 port ( dins2 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts2 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter3 port ( dins3 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts3 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter4 port ( dins4 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts4 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter5 port ( dins5 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts5 : out STD_LOGIC_VECTOR (25 downto 0)); end component; component subfilter6 port ( dins6 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts6 : out STD_LOGIC_VECTOR (25 downto 0)); end component; begin commut: process(c) variable i : integer := 0; begin if (rising_edge(c)) then case i is when 0 => commutator5 <= din; when 1 => commutator4 <= din; when 2 => commutator3 <= din; when 3 => commutator2 <= din; when 4 => commutator1 <= din; when 5 => commutator0 <= din; sumsig <= signed(sumsig1) + signed(sumsig2) + signed(sumsig3) + signed(sumsig4) + signed(sumsig5) + signed(sumsig6); dout <= sumsig; when others => null; end case; if ( i < 6 ) then i := i + 1; else i := 0; end if; end if; end process commut; c1: subfilter1 port map ( dins1 => commutator0, douts1 => sumsig1, r => r, c => c ); c2: subfilter2 port map ( dins2 => commutator1, douts2 => sumsig2, r => r, c => c ); c3: subfilter3 port map ( dins3 => commutator2, douts3 => sumsig3, r => r, c => c ); c4: subfilter4 port map ( dins4 => commutator3, douts4 => sumsig4, r => r, c => c ); c5: subfilter5 port map ( dins5 => commutator4, douts5 => sumsig5, r => r, c => c ); c6: subfilter6 port map ( dins6 => commutator5, douts6 => sumsig6, r => r, c => c ); end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter1 is port ( dins1 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts1 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter1; architecture behavioral of subfilter1 is constant h10: std_logic_vector ( 12 downto 0 ) := "1111111111000"; constant h11: std_logic_vector ( 12 downto 0 ) := "0000000000001"; constant h12: std_logic_vector ( 12 downto 0 ) := "0000001110001"; constant h13: std_logic_vector ( 12 downto 0 ) := "1111010101101"; constant h14: std_logic_vector ( 12 downto 0 ) := "0001001000100"; constant h15: std_logic_vector ( 12 downto 0 ) := "0100000000000"; constant h16: std_logic_vector ( 12 downto 0 ) := "0001001000100"; constant h17: std_logic_vector ( 12 downto 0 ) := "1111010101101"; constant h18: std_logic_vector ( 12 downto 0 ) := "0000001110001"; constant h19: std_logic_vector ( 12 downto 0 ) := "0000000000001"; signal x10,x11,x12,x13,x14,x15,x16,x17,x18,x19: std_logic_vector ( 12 downto 0 ); signal m10,m11,m12,m13,m14,m15,m16,m17,m18,m19 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg1 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline1: process(c) variable i1 :integer := 0; begin if ( rising_edge(c) ) then m10 <= signed(x10)*signed(h10); m11 <= signed(m10) + signed(x11)*signed(h11); m12 <= signed(m11) + signed(x12)*signed(h12); m13 <= signed(m12) + signed(x13)*signed(h13); m14 <= signed(m13) + signed(x14)*signed(h14); m15 <= signed(m14) + signed(x15)*signed(h15); m16 <= signed(m15) + signed(x16)*signed(h16); m17 <= signed(m16) + signed(x17)*signed(h17); m18 <= signed(m17) + signed(x18)*signed(h18); m19 <= signed(m18) + signed(x19)*signed(h19); dout_reg1 <= m19; end if; end process pipeline1; fir1: process(r,c) begin if r='1' then x10 <= (others=>'0'); x11 <= (others=>'0'); x12 <= (others=>'0'); x13 <= (others=>'0'); x14 <= (others=>'0'); x15 <= (others=>'0'); x16 <= (others=>'0'); x17 <= (others=>'0'); x18 <= (others=>'0'); x19 <= (others=>'0'); elsif (rising_edge(c)) then douts1 <= dout_reg1; x10( 12 downto 0 ) <= dins1( 12 downto 0 ); x11( 12 downto 0 ) <= x10( 12 downto 0 ); x12( 12 downto 0 ) <= x11( 12 downto 0 ); x13( 12 downto 0 ) <= x12( 12 downto 0 ); x14( 12 downto 0 ) <= x13( 12 downto 0 ); x15( 12 downto 0 ) <= x14( 12 downto 0 ); x16( 12 downto 0 ) <= x15( 12 downto 0 ); x17( 12 downto 0 ) <= x16( 12 downto 0 ); x18( 12 downto 0 ) <= x17( 12 downto 0 ); x19( 12 downto 0 ) <= x18( 12 downto 0 ); end if; end process fir1; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter2 is port ( dins2 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts2 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter2; architecture behavioral of subfilter2 is constant h20: std_logic_vector ( 12 downto 0 ) := "1111111001110"; constant h21: std_logic_vector ( 12 downto 0 ) := "0000000100001"; constant h22: std_logic_vector ( 12 downto 0 ) := "0000001000101"; constant h23: std_logic_vector ( 12 downto 0 ) := "1111010011101"; constant h24: std_logic_vector ( 12 downto 0 ) := "0001110011110"; constant h25: std_logic_vector ( 12 downto 0 ) := "0011111001001"; constant h26: std_logic_vector ( 12 downto 0 ) := "0000100001001"; constant h27: std_logic_vector ( 12 downto 0 ) := "1111011101011"; constant h28: std_logic_vector ( 12 downto 0 ) := "0000010000011"; constant h29: std_logic_vector ( 12 downto 0 ) := "1111111101001"; signal x20,x21,x22,x23,x24,x25,x26,x27,x28,x29: std_logic_vector ( 12 downto 0 ); signal m20,m21,m22,m23,m24,m25,m26,m27,m28,m29 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg2 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline2: process(c) variable i2 : integer := 0; begin if ( rising_edge(c) ) then m20 <= signed(x20)*signed(h20); m21 <= signed(m20) + signed(x21)*signed(h21); m22 <= signed(m21) + signed(x22)*signed(h22); m23 <= signed(m22) + signed(x23)*signed(h23); m24 <= signed(m23) + signed(x24)*signed(h24); m25 <= signed(m24) + signed(x25)*signed(h25); m26 <= signed(m25) + signed(x26)*signed(h26); m27 <= signed(m26) + signed(x27)*signed(h27); m28 <= signed(m27) + signed(x28)*signed(h28); m29 <= signed(m28) + signed(x29)*signed(h29); dout_reg2 <= m29; end if; end process pipeline2; fir2: process(r,c) begin if r='1' then x20 <= (others=>'0'); x21 <= (others=>'0'); x22 <= (others=>'0'); x23 <= (others=>'0'); x24 <= (others=>'0'); x25 <= (others=>'0'); x26 <= (others=>'0'); x27 <= (others=>'0'); x28 <= (others=>'0'); x29 <= (others=>'0'); elsif (rising_edge(c)) then douts2 <= dout_reg2; x20( 12 downto 0 ) <= dins2( 12 downto 0 ); x21( 12 downto 0 ) <= x20( 12 downto 0 ); x22( 12 downto 0 ) <= x21( 12 downto 0 ); x23( 12 downto 0 ) <= x22( 12 downto 0 ); x24( 12 downto 0 ) <= x23( 12 downto 0 ); x25( 12 downto 0 ) <= x24( 12 downto 0 ); x26( 12 downto 0 ) <= x25( 12 downto 0 ); x27( 12 downto 0 ) <= x26( 12 downto 0 ); x28( 12 downto 0 ) <= x27( 12 downto 0 ); x29( 12 downto 0 ) <= x28( 12 downto 0 ); end if; end process fir2; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter3 is port ( dins3 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts3 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter3; architecture behavioral of subfilter3 is constant h30: std_logic_vector ( 12 downto 0 ) := "1111111011111"; constant h31: std_logic_vector ( 12 downto 0 ) := "0000001000101"; constant h32: std_logic_vector ( 12 downto 0 ) := "1111111111110"; constant h33: std_logic_vector ( 12 downto 0 ) := "1111011001011"; constant h34: std_logic_vector ( 12 downto 0 ) := "0010011110110"; constant h35: std_logic_vector ( 12 downto 0 ) := "0011100101000"; constant h36: std_logic_vector ( 12 downto 0 ) := "0000000000010"; constant h37: std_logic_vector ( 12 downto 0 ) := "1111101000100"; constant h38: std_logic_vector ( 12 downto 0 ) := "0000001111101"; constant h39: std_logic_vector ( 12 downto 0 ) := "1111111011100"; signal x30,x31,x32,x33,x34,x35,x36,x37,x38,x39: std_logic_vector ( 12 downto 0 ); signal m30,m31,m32,m33,m34,m35,m36,m37,m38,m39 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg3 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline3: process(c) variable i3: integer := 0; begin if ( rising_edge(c) ) then m30 <= signed(x30)*signed(h30); m31 <= signed(m30) + signed(x31)*signed(h31); m32 <= signed(m31) + signed(x32)*signed(h32); m33 <= signed(m32) + signed(x33)*signed(h33); m34 <= signed(m33) + signed(x34)*signed(h34); m35 <= signed(m34) + signed(x35)*signed(h35); m36 <= signed(m35) + signed(x36)*signed(h36); m37 <= signed(m36) + signed(x37)*signed(h37); m38 <= signed(m37) + signed(x38)*signed(h38); m39 <= signed(m38) + signed(x39)*signed(h39); dout_reg3 <= m39; end if; end process pipeline3; fir3: process(r,c) begin if r='1' then x30 <= (others=>'0'); x31 <= (others=>'0'); x32 <= (others=>'0'); x33 <= (others=>'0'); x34 <= (others=>'0'); x35 <= (others=>'0'); x36 <= (others=>'0'); x37 <= (others=>'0'); x38 <= (others=>'0'); x39 <= (others=>'0'); elsif (rising_edge(c)) then douts3 <= dout_reg3; x30( 12 downto 0 ) <= dins3( 12 downto 0 ); x31( 12 downto 0 ) <= x30( 12 downto 0 ); x32( 12 downto 0 ) <= x31( 12 downto 0 ); x33( 12 downto 0 ) <= x32( 12 downto 0 ); x34( 12 downto 0 ) <= x33( 12 downto 0 ); x35( 12 downto 0 ) <= x34( 12 downto 0 ); x36( 12 downto 0 ) <= x35( 12 downto 0 ); x37( 12 downto 0 ) <= x36( 12 downto 0 ); x38( 12 downto 0 ) <= x37( 12 downto 0 ); x39( 12 downto 0 ) <= x38( 12 downto 0 ); end if; end process fir3; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter4 is port ( dins4 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts4 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter4; architecture behavioral of subfilter4 is constant h40: std_logic_vector ( 12 downto 0 ) := "1111111010110"; constant h41: std_logic_vector ( 12 downto 0 ) := "0000001100110"; constant h42: std_logic_vector ( 12 downto 0 ) := "1111110100101"; constant h43: std_logic_vector ( 12 downto 0 ) := "1111101000001"; constant h44: std_logic_vector ( 12 downto 0 ) := "0011000101111"; constant h45: std_logic_vector ( 12 downto 0 ) := "0011000101111"; constant h46: std_logic_vector ( 12 downto 0 ) := "1111101000001"; constant h47: std_logic_vector ( 12 downto 0 ) := "1111110100101"; constant h48: std_logic_vector ( 12 downto 0 ) := "0000001100110"; constant h49: std_logic_vector ( 12 downto 0 ) := "1111111010110"; signal x40,x41,x42,x43,x44,x45,x46,x47,x48,x49: std_logic_vector ( 12 downto 0 ); signal m40,m41,m42,m43,m44,m45,m46,m47,m48,m49 : std_logic_vector ( 25 downto 0 ) ; signal dout_reg4 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline4: process(c) variable i4 : integer := 0; begin if ( rising_edge(c) ) then m40 <= signed(x40)*signed(h40); m41 <= signed(m40) + signed(x41)*signed(h41); m42 <= signed(m41) + signed(x42)*signed(h42); m43 <= signed(m42) + signed(x43)*signed(h43); m44 <= signed(m43) + signed(x44)*signed(h44); m45 <= signed(m44) + signed(x45)*signed(h45); m46 <= signed(m45) + signed(x46)*signed(h46); m47 <= signed(m46) + signed(x47)*signed(h47); m48 <= signed(m47) + signed(x48)*signed(h48); m49 <= signed(m48) + signed(x49)*signed(h49); dout_reg4 <= m49; end if; end process pipeline4; fir4: process(r,c) begin if r='1' then x40 <= (others=>'0'); x41 <= (others=>'0'); x42 <= (others=>'0'); x43 <= (others=>'0'); x44 <= (others=>'0'); x45 <= (others=>'0'); x46 <= (others=>'0'); x47 <= (others=>'0'); x48 <= (others=>'0'); x49 <= (others=>'0'); elsif (rising_edge(c)) then douts4 <= dout_reg4; x40( 12 downto 0 ) <= dins4( 12 downto 0 ); x41( 12 downto 0 ) <= x40( 12 downto 0 ); x42( 12 downto 0 ) <= x41( 12 downto 0 ); x43( 12 downto 0 ) <= x42( 12 downto 0 ); x44( 12 downto 0 ) <= x43( 12 downto 0 ); x45( 12 downto 0 ) <= x44( 12 downto 0 ); x46( 12 downto 0 ) <= x45( 12 downto 0 ); x47( 12 downto 0 ) <= x46( 12 downto 0 ); x48( 12 downto 0 ) <= x47( 12 downto 0 ); x49( 12 downto 0 ) <= x48( 12 downto 0 ); end if; end process fir4; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter5 is port ( dins5 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts5 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter5; architecture behavioral of subfilter5 is constant h50: std_logic_vector ( 12 downto 0 ) := "1111111011100"; constant h51: std_logic_vector ( 12 downto 0 ) := "0000001111101"; constant h52: std_logic_vector ( 12 downto 0 ) := "1111101000100"; constant h53: std_logic_vector ( 12 downto 0 ) := "0000000000010"; constant h54: std_logic_vector ( 12 downto 0 ) := "0011100101000"; constant h55: std_logic_vector ( 12 downto 0 ) := "0010011110110"; constant h56: std_logic_vector ( 12 downto 0 ) := "1111011001011"; constant h57: std_logic_vector ( 12 downto 0 ) := "1111111111110"; constant h58: std_logic_vector ( 12 downto 0 ) := "0000001000101"; constant h59: std_logic_vector ( 12 downto 0 ) := "1111111011111"; signal x50,x51,x52,x53,x54,x55,x56,x57,x58,x59: std_logic_vector ( 12 downto 0 ); signal m50,m51,m52,m53,m54,m55,m56,m57,m58,m59: std_logic_vector ( 25 downto 0 ) ; signal dout_reg5 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline5: process(c) variable i5 : integer := 0; begin if ( rising_edge(c) ) then m50 <= signed(x50)*signed(h50); m51 <= signed(m50) + signed(x51)*signed(h51); m52 <= signed(m51) + signed(x52)*signed(h52); m53 <= signed(m52) + signed(x53)*signed(h53); m54 <= signed(m53) + signed(x54)*signed(h54); m55 <= signed(m54) + signed(x55)*signed(h55); m56 <= signed(m55) + signed(x56)*signed(h56); m57 <= signed(m56) + signed(x57)*signed(h57); m58 <= signed(m57) + signed(x58)*signed(h58); m59 <= signed(m58) + signed(x59)*signed(h59); dout_reg5 <= m59; end if; end process pipeline5; fir5: process(r,c) begin if r='1' then x50 <= (others=>'0'); x51 <= (others=>'0'); x52 <= (others=>'0'); x53 <= (others=>'0'); x54 <= (others=>'0'); x55 <= (others=>'0'); x56 <= (others=>'0'); x57 <= (others=>'0'); x58 <= (others=>'0'); x59 <= (others=>'0'); elsif (rising_edge(c)) then douts5 <= dout_reg5; x50( 12 downto 0 ) <= dins5( 12 downto 0 ); x51( 12 downto 0 ) <= x50( 12 downto 0 ); x52( 12 downto 0 ) <= x51( 12 downto 0 ); x53( 12 downto 0 ) <= x52( 12 downto 0 ); x54( 12 downto 0 ) <= x53( 12 downto 0 ); x55( 12 downto 0 ) <= x54( 12 downto 0 ); x56( 12 downto 0 ) <= x55( 12 downto 0 ); x57( 12 downto 0 ) <= x56( 12 downto 0 ); x58( 12 downto 0 ) <= x57( 12 downto 0 ); x59( 12 downto 0 ) <= x58( 12 downto 0 ); end if; end process fir5; end behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity subfilter6 is port ( dins6 : in std_logic_vector ( 12 downto 0 ); r : in STD_LOGIC; c : in STD_LOGIC; douts6 : out STD_LOGIC_VECTOR (25 downto 0)); end subfilter6; architecture behavioral of subfilter6 is constant h60: std_logic_vector ( 12 downto 0 ) := "1111111101001"; constant h61: std_logic_vector ( 12 downto 0 ) := "0000010000011"; constant h62: std_logic_vector ( 12 downto 0 ) := "1111011101011"; constant h63: std_logic_vector ( 12 downto 0 ) := "0000100001001"; constant h64: std_logic_vector ( 12 downto 0 ) := "0011111001001"; constant h65: std_logic_vector ( 12 downto 0 ) := "0001110011110"; constant h66: std_logic_vector ( 12 downto 0 ) := "1111010011101"; constant h67: std_logic_vector ( 12 downto 0 ) := "0000001000101"; constant h68: std_logic_vector ( 12 downto 0 ) := "1111111110101"; constant h69: std_logic_vector ( 12 downto 0 ) := "1111111001110"; signal x60,x61,x62,x63,x64,x65,x66,x67,x68,x69: std_logic_vector ( 12 downto 0 ); signal m60,m61,m62,m63,m64,m65,m66,m67,m68,m69: std_logic_vector ( 25 downto 0 ) ; signal dout_reg6 : STD_LOGIC_VECTOR (25 downto 0); begin pipeline6: process(c) variable i6 : integer := 0; begin if ( rising_edge(c) ) then m60 <= signed(x60)*signed(h60); m61 <= signed(m60) + signed(x61)*signed(h61); m62 <= signed(m61) + signed(x62)*signed(h62); m63 <= signed(m62) + signed(x63)*signed(h63); m64 <= signed(m63) + signed(x64)*signed(h64); m65 <= signed(m64) + signed(x65)*signed(h65); m66 <= signed(m65) + signed(x66)*signed(h66); m67 <= signed(m66) + signed(x67)*signed(h67); m68 <= signed(m67) + signed(x68)*signed(h68); m69 <= signed(m68) + signed(x69)*signed(h69); dout_reg6 <= m69; end if; end process pipeline6; fir6: process(r,c) begin if r='1' then x60 <= (others=>'0'); x61 <= (others=>'0'); x62 <= (others=>'0'); x63 <= (others=>'0'); x64 <= (others=>'0'); x65 <= (others=>'0'); x66 <= (others=>'0'); x67 <= (others=>'0'); x68 <= (others=>'0'); x69 <= (others=>'0'); elsif (rising_edge(c)) then douts6 <= dout_reg6; x60( 12 downto 0 ) <= dins6( 12 downto 0 ); x61( 12 downto 0 ) <= x60( 12 downto 0 ); x62( 12 downto 0 ) <= x61( 12 downto 0 ); x63( 12 downto 0 ) <= x62( 12 downto 0 ); x64( 12 downto 0 ) <= x63( 12 downto 0 ); x65( 12 downto 0 ) <= x64( 12 downto 0 ); x66( 12 downto 0 ) <= x65( 12 downto 0 ); x67( 12 downto 0 ) <= x66( 12 downto 0 ); x68( 12 downto 0 ) <= x67( 12 downto 0 ); x69( 12 downto 0 ) <= x68( 12 downto 0 ); end if; end process fir6; end behavioral;