library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library peb_lib; use peb_lib.all; entity CBTLV3253_tb is end CBTLV3253_tb; architecture archi of CBTLV3253_tb is component CBTLV3253 port( inout_1B1 : inout real; inout_1B2 : inout real; inout_1B3 : inout real; inout_1B4 : inout real; in_1OEn : in std_logic; inout_1A : inout real; S1, S0 : in std_logic ); end component; signal inout_1B1_tb : real; signal inout_1B2_tb : real; signal inout_1B3_tb : real; signal inout_1B4_tb : real; signal in_1OEn_tb : std_logic; signal inout_1A_tb : real; signal S1_tb : std_logic; signal S0_tb : std_logic; begin uut: CBTLV3253 port map( inout_1B1 => inout_1B1_tb, inout_1B2 => inout_1B2_tb, inout_1B3 => inout_1B3_tb, inout_1B4 => inout_1B4_tb, in_1OEn => in_1OEn_tb, inout_1A => inout_1A_tb, S1 => S1_tb, S0 => S0_tb ); stimuli: process begin in_1OEn_tb <= '1'; inout_1B1_tb <= 1.0; inout_1B2_tb <= 2.0; inout_1B3_tb <= 3.0; inout_1B4_tb <= 4.0; S1_tb <= '0'; S0_tb <= '0'; wait for 100 ns; in_1OEn_tb <= '0'; --OEn_2_tb <= '0'; S1_tb <= '0'; S0_tb <= '0'; wait for 100 ns; S1_tb <= '1'; S0_tb <= '0'; wait for 100 ns; S1_tb <= '0'; S0_tb <= '1'; wait for 100 ns; S1_tb <= '1'; S0_tb <= '1'; wait for 100 ns; assert false report "NONE. End of simulation." severity failure; wait for 100 us; end process stimuli; end archi;