module divider( output reg[7:0] q, // catul impartirii output reg[7:0] r, // restul impartirii input[7:0] a, b); reg[7:0] w [0:8]; reg[7:0] Q [0:8]; reg[7:0] QM [0:8]; reg[3:0] i; always @(*) begin q=0; r=0; Q[0]=0; QM[0]=0; w[0]=a; for (i=1; i<=7; i=i+1) begin w[i]=2*w[i-1]; if (w[i]>=0.5) begin w[i]=w[i]-b; q[i]=1; Q[i]=Q[i-1]+2**(-i); QM[i]=Q[i-1]; end else if (w[i]<-0.5) begin w[i]=w[i]+b; q[i]=-1; Q[i]=QM[i-1]+2**(-i); QM[i]=QM[i-1]; end else q[i]=0; Q[i]=Q[i-1]; QM[i]=QM[i-1]+2**(-i); end end endmodule