library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; --use work.type_def_pack.all; -------------------------- -------------------------- package type_def_pack is constant s is integer range 1 to 5 := 1; constant line_width is integer range 0 to 31 := 8; type wire is array (0 to 2**s -1) of std_logic_vector(line_width-1 downto 0); end package; -------------------------- -------------------------- entity Generic_Mux is --s : integer := 3; generic ( line_width : integer := 8); port ( Dinput : in wire; sel : in std_logic_vector (s-1 downto 0); output : out std_logic_vector(line_width-1 downto 0)); end Generic_Mux; ------------------------- ------------------------- architecture behavioral of Generic_Mux is --TYPE Darray IS ARRAY (line_width-1 downto 0) OF std_logic_vector (2**s -1 downto 0); --SIGNAL input : Darray; BEGIN -- Rows : FOR i IN 0 TO line_width-1 GENERATE -- Columns: FOR j IN 0 TO 2**s -1 GENERATE -- input(i)(j) <= Dinput( (j-1) * (line_width-1) + i ); -- END GENERATE; -- END GENERATE; output <= Dinput(conv_integer(sel))(line_width-1 downto 0); END architecture behavioral;