---------------------------------------------------------------------------------- -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top_3_28_A is Port ( in_1 : in STD_LOGIC; in_2 : in STD_LOGIC; out_1 : out STD_LOGIC; out_2 : out STD_LOGIC; led1 : out STD_LOGIC; led0 : out STD_LOGIC ); end entity; architecture basic of top_3_28_A is begin top_behavior : process is begin if in_1 = '1' then out_1 <= '1' after 2ns ; endif; if in_1 = '0' then out_1 <= '0' after 2ns ; endif; if in_2 = '1' then out_2 <= '1' after 2ns ; endif; if in_2 = '0' then out_2 <= '0' after 2ns ; end if; end process top_behavior ; ************** line 48 end architecture basic; ************** line 50 entity test_bench is end entity test_bench; architecture test_top_3_28_A of test_bench is signal in_1, in_2, out_1, out_2; begin dut:entity work.top_3_28_A(behav) port (in_1, in_2, out_1, out_2 ); *************** lin1 62 stimulus : process is begin out_1 <= '0'; out_2 <= '0'; wait for 100 ms; loop in_1 <= '0'; in_2 <= '0'; wait for 1000 ms; in_1 <= '1'; in_2 <= '1'; wait for 1000 ms; end loop; end process stimulus; ************** line 77 end architecture test_top_3_28_A ; ************** line 78 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Error (10500): VHDL syntax error at top_3_28_A.vhd(48) near text "process"; expecting "if" Error (10500): VHDL syntax error at top_3_28_A.vhd(50) near text "architecture"; expecting "if" Error (10500): VHDL syntax error at top_3_28_A.vhd(61) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at top_3_28_A.vhd(62) near text ";"; expecting ":=", or "<=" Error (10500): VHDL syntax error at top_3_28_A.vhd(78) near text "process"; expecting "if" Error (10500): VHDL syntax error at top_3_28_A.vhd(79) near text "architecture"; expecting "if" Info (12021): Found 0 design units, including 0 entities, in source file top_3_28_a.vhd Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings Error: Peak virtual memory: 467 megabytes Error: Processing ended: Fri Mar 29 15:04:51 2013 Error: Elapsed time: 00:00:02 Error: Total CPU time (on all processors): 00:00:02