--------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:55:56 02/12/2013 -- Design Name: -- Module Name: 4_bit_full_adder_sub - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity four_bit_full_adder_sub is Port ( M : in STD_LOGIC_VECTOR (3 downto 0); N : in STD_LOGIC_VECTOR (3 downto 0); SO : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0); COUT : out STD_LOGIC); end four_bit_full_adder_sub; architecture Behavioral of four_bit_full_adder_sub is signal xor_out:STD_LOGIC_VECTOR(3 downto 0); signal cout_adder:STD_LOGIC_VECTOR(2 downto 0); component xor_gate is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC ); end component; component full_adder is Port ( a : in STD_LOGIC_VECTOR (1 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC; cout : out STD_LOGIC); end component; begin XORG1: xor_gate port map (y=>N(0),x=>SO,z=>xor_out(0)); XORG2: xor_gate port map (y=>N(1),x=>SO,z=>xor_out(1)); XORG3: xor_gate port map (y=>N(2),x=>SO,z=>xor_out(2)); XORG4: xor_gate port map (y=>N(3),x=>SO,z=>xor_out(3)); F_ADDER1: full_adder port map (a(1)=>M(0),a(0)=>xor_out(0),cin=>SO,s=>S(0),cout=>cout_adder(0)); F_ADDER2: full_adder port map (a(1)=>M(1),a(0)=>xor_out(1),s=>S(1),cin=>cout_adder(0),cout=>cout_adder(1)); F_ADDER3: full_adder port map (a(1)=>M(2),a(0)=>xor_out(2),s=>S(2),cin=>cout_adder(1),cout=>cout_adder(2)); F_ADDER4: full_adder port map (a(1)=>M(3),a(0)=>xor_out(3),s=>S(3),cin=>cout_adder(2),cout=>COUT); end Behavioral;